Datasheet

ADS1217
SBAS260C
7
www.ti.com
SPEC DESCRIPTION MIN MAX UNITS
t
1
SCLK Period 4t
OSC
Periods
3 DRDY Periods
t
2
SCLK Pulse Width, HIGH and LOW 200 ns
t
3
CS LOW to First SCLK Edge; Setup Time
(1)
0ns
t
4
D
IN
Valid to SCLK Edge; Setup Time 50 ns
t
5
Valid D
IN
to SCLK Edge; Hold Time 50 ns
t
6
Delay Between Last SCLK Edge for D
IN
and First SCLK
Edge for D
OUT
:
RDATA, RDATAC, RREG, WREG, RRAM, WRAM 50 t
OSC
Periods
CSREG, CSRAMX, CSRAM 200 t
OSC
Periods
CSARAM, CSARAMX 1100 t
OSC
Periods
t
7
(2)
SCLK Edge to Valid New D
OUT
50 ns
t
8
(2)
SCLK Edge to D
OUT
, Hold Time 0 ns
t
9
Last SCLK Edge to D
OUT
Tri-State 6 10 t
OSC
Periods
NOTE: D
OUT
goes tri-state immediately when CS goes HIGH.
t
10
CS LOW Time After Final SCLK Edge 0 ns
t
11
Final SCLK Edge of One Op Code Until First Edge SCLK
of Next Command:
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, t
OSC
Periods
CSRAM, CSARAM, CSREG, DSYNC, SLEEP, RDATA,
RDATAC, STOPC 4 t
OSC
Periods
CREG, CRAM 220 t
OSC
Periods
CREGA 1600 t
OSC
Periods
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 7 DRDY Periods
SELFCAL 14 DRDY Periods
RESET (Input pin, command, or SCLK pattern) 16 t
OSC
Periods
t
12
300 500 t
OSC
Periods
t
13
5t
OSC
Periods
t
14
550 750 t
OSC
Periods
t
15
1050 1250 t
OSC
Periods
t
16
Pulse Width 4t
OSC
Periods
t
17
Data Not Valid 4 t
OSC
Periods
NOTES: (1) CS may be tied LOW. (2) Load = 20pF.
TIMING DIAGRAMS
TIMING CHARACTERISTICS
t
4
MSB
(Command or Command and Data)
LSB
t
5
t
1
t
3
CS
SCLK
(POL = 0)
D
IN
D
OUT
NOTE: (1) Bit Order = 0.
SCLK Reset Waveform
t
7
MSB
(1)
LSB
(1)
t
8
t
10
t
2
t
2
t
11
t
6
t
9
SCLK
(POL = 1)
t
12
t
14
t
15
t
13
t
13
SCLK
t
17
DRDY
t
16
RESET, DSYNC, PDWN
ADS1217
Resets On
Falling Edge