Datasheet

ADS1217
14
SBAS260C
www.ti.com
DIGITAL I/O INTERFACE
The ADS1217 has eight pins dedicated for digital I/O. The
default power-up condition for the digital I/O pins are as inputs.
All of the digital I/O pins are individually configurable as inputs
or outputs. They are configured through the DIR control regis-
ter. The DIR register defines whether the pin is an input or
output, and the DIO register defines the state of the digital
output. When the digital I/O are configured as inputs, DIO is
used to read the state of the pin. If the digital I/O are not used,
either 1) configure as outputs; or, 2) leave as inputs and tie to
ground, this prevents excess power dissipation.
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) allows a controller to
communicate synchronously with the ADS1217. The ADS1217
operates in slave only mode.
Chip Select ( CS )
The chip select ( CS ) input of the ADS1217 must be exter-
nally asserted before a master device can exchange data
with the ADS1217.
CS must be LOW for the duration of the
transaction.
CS can be tied low.
Serial Clock (SCLK)
SCLK, a Schmitt Trigger input, clocks data transfer on the D
IN
input and D
OUT
output. When transferring data to or from the
ADS1217, multiple bits of data may be transferred back-to-
back with no delay in SCLKs or toggling of
CS . Make sure
to avoid glitches on SCLK as they can cause extra shifting of
the data.
Polarity (POL)
The serial clock polarity is specified by the POL input. When
SCLK is active HIGH, set POL HIGH. When SCLK is active
LOW, set POL LOW.
DATA READY
The DRDY output is used as a status signal to indicate when
data is ready to be read from the ADS1217.
DRDY goes LOW
when new data is available. It is reset HIGH when a read
operation from the data register is complete. It also goes HIGH
prior to the updating of the output register to indicate when not
to read from the device to ensure that a data read is not
attempted while the register is being updated.
DSYNC OPERATION
DSYNC is used to provide for synchronization of the A/D
conversion with an external event. Synchronization can be
achieved either through the
DSYNC pin or the DSYNC
command. When the
DSYNC pin is used, the filter counter is
reset on the falling edge of
DSYNC . The modulator is held in
reset until
DSYNC is taken HIGH. Synchronization occurs on
the next rising edge of the system clock after
DSYNC is
taken HIGH.
FIGURE 4. Filter Frequency Responses.
SINC
3
FILTER RESPONSE
(1)
(–3dB = 0.262 • f
DATA
= 15.76Hz)
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
0 30 12060 90 150 180 210 240 270 300
Gain (dB)
SINC
2
FILTER RESPONSE
(1)
(–3dB = 0.318 • f
DATA
= 19.11Hz)
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
0 30 12060 90 150 180 210 240 270 300
Gain (dB)
FAST SETTLING FILTER RESPONSE
(1)
(–3dB = 0.469 • f
DATA
= 28.125Hz)
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
0
NOTE: (1) f
DATA
= 60Hz.
30 12060 90 150 180 210 240 270 300
Gain (dB)