Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 48

8-Channel, 24-Bit

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● 24 BITS NO MISSING CODES

● INL: 0.0012% of FSR (max)

● FULL-SCALE INPUT: ±2V

REF

● PGA FROM 1 TO 128

● 22 BITS EFFECTIVE RESOLUTION

(PGA = 1), 19 BITS (PGA = 128)

● SINGLE CYCLE SETTLING MODE

● PROGRAMMABLE DATA OUTPUT RATES

UP TO 1kHz

● ON-CHIP 1.25V/2.5V REFERENCE

● ON-CHIP CALIBRATION

● SPI COMPATIBLE

● POWER SUPPLY: 2.7V to 5.25V

● < 1mW POWER CONSUMPTION, V

= 3V

DESCRIPTION

The ADS1217 is a precision, wide dynamic range, delta-

sigma, Analog-to-Digital (A/D) converter with 24-bit resolu-

tion operating from 2.7V to 5.25V supplies. The delta-sigma,

A/D converter provides up to 24 bits of no missing code

performance and effective resolution of 22 bits.

The eight input channels are multiplexed. Internal buffering

can be selected to provide a very high input impedance for

direct connection to transducers or low-level voltage signals.

Burnout current sources are provided that allow for the

detection of an open or shorted sensor. An 8-bit Digital-to-

Analog Converter (DAC) provides an offset correction with a

range of 50% of the FSR (Full-Scale Range).

The PGA (Programmable Gain Amplifier) provides selectable

gains of 1 to 128 with an effective resolution of 19 bits at a gain

of 128. The A/D conversion is accomplished with a 2nd-order,

delta-sigma modulator and programmable sinc filter. The

reference input is differential and can be used for ratiometric

measurements. The onboard current DACs operate indepen-

dently with the maximum current set by an external resistor.

The serial interface is SPI compatible. Eight bits of digital I/O

are also provided that can be used for input or output. The

ADS1217 is designed for high-resolution measurement appli-

cations in smart transmitters, industrial process control, weigh

scales, chromatography, and portable instrumentation.

APPLICATIONS

● INDUSTRIAL PROCESS CONTROL

● LIQUID/GAS CHROMATOGRAPHY

● BLOOD ANALYSIS

● SMART TRANSMITTERS

● PORTABLE INSTRUMENTATION

● WEIGH SCALES

● PRESSURE TRANSDUCERS

BUF PGA

Voltage

Reference

Clock Generator

Registers

Serial Interface

2nd-Order

Modulator

RAM

Digital I/O

Interface

AGND AV

DAC

REFOUT

RCAP

REF+

REF–

OUT

D7BUFEN ...D0DGNDDV

SCLK

POL

OUT

DRDY

PDWN

DYSNC

RESET

MUX

INCOM

IDAC1

Controller

Program-

mable

Digital

Filter

8-Bit

IDAC

IDAC2

8-Bit

IDAC

Offset

DAC

ADS1217

SBAS260C – MAY 2002 – REVISED FEBRUARY 2007

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

Summary of content (33 pages)

PAGE 1
ADS1217 ADS 121 7 SBAS260C – MAY 2002 – REVISED FEBRUARY 2007 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● ● The ADS1217 is a precision, wide dynamic range, deltasigma, Analog-to-Digital (A/D) converter with 24-bit resolution operating from 2.7V to 5.25V supplies. The delta-sigma, A/D converter provides up to 24 bits of no missing code performance and effective resolution of 22 bits. ● ● ● ● ● ● ● 24 BITS NO MISSING CODES INL: 0.
PAGE 2
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY AVDD to AGND ...................................................................... –0.3V to +6V DVDD to DGND ...................................................................... –0.3V to +6V Input Current ............................................................... 100mA, Momentary Input Current ................................................................. 10mA, Continuous AIN ........................................................
PAGE 3
ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.) All specifications at –40°C to +85°C, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified.
PAGE 4
ELECTRICAL CHARACTERISTICS: AVDD = 3V All specifications at –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA = 10Hz, and VREF = +1.25V, unless otherwise specified.
PAGE 5
ELECTRICAL CHARACTERISTICS: AVDD = 3V (Cont.) All specifications at –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA = 10Hz, and VREF = +1.25V, unless otherwise specified.
PAGE 6
PIN CONFIGURATION DIN SCLK CS DRDY DVDD DGND DSYNC POL PDWN XOUT XIN TQFP DOUT Top View 36 35 34 33 32 31 30 29 28 27 26 25 D0 37 24 RESET D1 38 23 BUFEN D2 39 22 DGND D3 40 21 DGND D4 41 20 DGND D5 42 19 DGND ADS1217 D6 43 18 DGND D7 44 17 RDAC 5 6 7 8 9 10 11 12 AGND 4 AINCOM 3 AIN7 2 AIN4 1 AIN6 13 AVDD AIN5 VREF– 48 AIN3 14 VRCAP AIN2 VREF+ 47 AIN1 15 IDAC1 AIN0 VREFOUT 46 AGND 16 IDAC2 AVDD AGND 45 PIN DESCRIPTIONS PIN NUMBER N
PAGE 7
TIMING DIAGRAMS CS t3 t1 t2 t10 SCLK (POL = 0) SCLK (POL = 1) t4 DIN MSB t2 t6 t5 t11 LSB (Command or Command and Data) t7 DOUT t8 MSB(1) t9 LSB(1) NOTE: (1) Bit Order = 0.
PAGE 8
TYPICAL CHARACTERISTICS AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified.
PAGE 9
TYPICAL CHARACTERISTICS (Cont.) AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. COMMON-MODE REJECTION RATIO vs FREQUENCY NOISE vs INPUT SIGNAL 0.7 0.5 CMRR (dB) Noise (rms, ppm of FS) 0.6 0.4 0.3 0.2 0.
PAGE 10
TYPICAL CHARACTERISTICS (Cont.) AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified.
PAGE 11
TYPICAL CHARACTERISTICS (Cont.) AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. OFFSET DAC: GAIN vs TEMPERATURE IDAC IOUT vs VOUT 1.00020 1.0000 1.00016 +85°C 1.000 1.00008 IOUT (Normalized) Normalized Gain 1.00012 1.00004 1.00000 0.99996 0.99992 0.99988 +25°C 0.999 0.999 0.99984 –40°C 0.99980 0.99976 –50 –30 –10 10 30 50 70 0.
PAGE 12
OVERVIEW BURNOUT CURRENT SOURCES INPUT MULTIPLEXER The input multiplexer (mux) provides for any combination of differential inputs to be selected on any of the input channels, as shown in Figure 1. If channel 1 is selected as the positive differential input channel, any other channel can be selected as the negative differential input channel. With this method, it is possible to have up to eight fully differential input channels.
PAGE 13
VOLTAGE REFERENCE INPUT The ADS1217 uses a differential voltage reference input. The input signal is measured against the differential voltage VREF ≡ (VREF+) – (VREF–). For AVDD = 5V, VREF is typically 2.5V. For AVDD = 3V, VREF is typically 1.25V. Due to the sampling nature of the modulator, the reference input current increases with higher modulator clock frequency (fMOD) and higher PGA settings. ON-CHIP VOLTAGE REFERENCE A selectable voltage reference (1.25V or 2.
PAGE 14
SINC2 FILTER RESPONSE(1) (–3dB = 0.318 • fDATA = 19.11Hz) 0 0 –20 –20 –40 –40 Gain (dB) Gain (dB) SINC3 FILTER RESPONSE(1) (–3dB = 0.262 • fDATA = 15.76Hz) –60 –60 –80 –80 –100 –100 –120 –120 0 30 60 90 120 150 180 210 240 270 300 0 30 60 90 Frequency (Hz) 120 150 180 210 240 270 300 Frequency (Hz) FAST SETTLING FILTER RESPONSE(1) (–3dB = 0.469 • fDATA = 28.
PAGE 15
When the DSYNC command is sent, the filter counter is reset on the edge of the last SCLK on the DSYNC command. The modulator is held in reset until the next edge of SCLK is detected. Synchronization occurs on the next rising edge of the system clock after the first SCLK after the DSYNC command. After a DSYNC operation, DRDY is held HIGH until valid data is ready.
PAGE 16
REGISTER MAP ADDRESS REGISTER BIT 7 00H SETUP ID 01H MUX PSEL3 02H ACR BOCS 03H IDAC1 04H 05H BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ID ID SPEED REF EN REF HI BUF EN BIT ORDER PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0 IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0 PGA2 PGA1 PGA0 IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0 IDAC2 IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC2_3 IDAC2_2 IDAC2_1 IDAC2_0 ODAC SIGN OSET_6 OSET_5 OSET_4 OSET_3 OSET_2
PAGE 17
ACR (Address 02H) Analog Control Register Reset Value = 00H bit 7 BOCS bit 7 bit 6 bit 5 bit 4 IDAC2R1 IDAC2R0 IDAC1R1 ODAC (Address 05H) Offset DAC Setting Reset Value = 00H bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IDAC1R0 PGA2 PGA1 PGA0 SIGN OSET6 OSET5 OSET4 OSET3 OSET2 OSET1 OSET0 BOCS: Burnout Current Source 0 = Disabled (default) 1 = Enabled ( bit 7 1 = Negative )  VREF  RANGE−1 (DAC Code) IDAC Current =   2  8RDAC  bit 6-5 bit
PAGE 18
M/DEC1 (Address 09H) Mode and Decimation Register Reset Value = 07H bit 7 bit 6 DRDY U/B bit 5 bit 4 SMODE1 SMODE0 bit 3 bit 2 bit 1 bit 0 Reserved DEC10 DEC09 DEC08 bit 7 DRDY: Data Ready (Read Only) This bit duplicates the state of the DRDY pin.
PAGE 19
COMMAND DEFINITIONS Operands: The commands listed below control the operation of the ADS1217. Some of the commands are stand-alone commands (e.g., RESET) while others require additional bytes (e.g., WREG requires command, count, and the data bytes). Commands that output data require a minimum of four fOSC cycles before the data is ready (e.g., RDATA).
PAGE 20
STOPC Stop Continuous Description: Ends the continuous data output mode. CREG Copy Registers to RAM Bank Operands: None Bytes: 1 Description: Copy the 16 control registers to the RAM bank specified in the op code. Refer to timing specifications for command execution time.
PAGE 21
WRAM Write to RAM Description: Write up to 128 RAM locations starting at the beginning of the RAM bank specified as part of the instruction. The number of bytes written is RAM is one plus the value of the second byte. Calculate the Checksum for all RAM Banks CSARAMX Operands: a, n Description: Calculate the checksum of all RAM Banks. The checksum is calculated as a sum of all the bytes with the carry ignored. The ID, DRDY, and DIO bits are masked so they are not included in the checksum.
PAGE 22
Calculate Checksum for all RAM Banks CSARAM Description: Calculate the checksum of all RAM Banks. The checksum is calculated as a sum of all the bytes with the carry ignored. All bits are included in the checksum calculation, there is no masking of bits. SELFGCAL Gain Self Calibration Description: Starts the process of self-calibration for gain. The Full-Scale Register (FSR) is updated with new values after this operation.
PAGE 23
WAKEUP Wakeup From Sleep Mode Sync DRDY DSYNC Description: Synchronizes the ADS1217 to the serial clock edge. Description: Use this command to wake up from sleep mode. Operands: None Operands: None Bytes: 1 Bytes: 1 Encoding: 1111 1011 Encoding: 1111 1100 Data Transfer Sequence: Data Transfer Sequence: 1111 1011 DIN 1111 1100 DIN RESET SLEEP Sleep Mode Reset to Power-Up Values Description: Restore the registers to their power-up values.
PAGE 24
DEFINITION OF TERMS BITS rms BIPOLAR Vrms Analog Input Voltage—the voltage at any one analog input relative to AGND.  4VREF     PGA  Conversion Cycle—the term conversion cycle usually refers to a discrete A/D conversion operation, such as that performed by a successive approximation converter. As used here, a conversion cycle refers to the tDATA time period. However, each digital output is actually based on the modulator results from several tDATA time periods.
PAGE 25
Full-Scale Range (FSR)—as with most A/D converters, the full-scale range of the ADS1217 is defined as the “input”, which produces the positive full-scale digital output minus the “input”, which produces the negative full-scale digital output. The full-scale range changes with gain setting, see Table V. For example, when the converter is configured with a 2.5V reference and is placed in a gain setting of 2, the full-scale range is: 2 • [1.25V (positive full-scale) minus –1.25V (negative full-scale)] = 5V.
PAGE 26
Revision History DATE REVISION PAGE SECTION DESCRIPTION 2/07 C 2,4 Electrical Characteristics Changed Gain Error condition from “Before Calibration” to “After Calibration” NOTE: Page numbers for previous revisions may differ from page numbers in the current version. ADS1217 26 www.ti.
PAGE 27
PACKAGE OPTION ADDENDUM www.ti.
PAGE 28
PACKAGE OPTION ADDENDUM www.ti.
PAGE 29
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1217IPFBR TQFP PFB 48 2000 330.0 16.8 9.6 9.6 1.5 12.0 16.0 Q2 ADS1217IPFBT TQFP PFB 48 250 177.8 16.4 9.6 9.6 1.5 12.0 16.
PAGE 30
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1217IPFBR TQFP PFB 48 2000 367.0 367.0 38.0 ADS1217IPFBT TQFP PFB 48 250 210.0 185.0 35.
PAGE 31
MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
PAGE 32
PAGE 33
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.