Datasheet

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TIMING CHARACTERISTICS
t
4
MSB
(CommandorCommandandData)
LSB
t
5
t
1
t
3
CS
SCLK
(POL=0)
D
IN
D
OUT
NOTE:(1)BitOrder=0.
t
7
MSB
(1)
LSB
(1)
t
8
t
10
t
2
t
2
t
11
t
6
t
9
SCLK
(POL=1)
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
SPEC DESCRIPTION MIN MAX UNITS
SCLK period 4 t
OSC
periods
t
1
3 DRDY periods
t
2
SCLK pulse width, HIGH and LOW 200 ns
t
3
CS LOW to first SCLK edge; setup time 0 ns
t
4
D
IN
valid to SCLK edge; setup time 50 ns
t
5
Valid D
IN
to SCLK edge; hold time 50 ns
Delay between last SCLK edge for D
IN
and first SCLK edge for D
OUT
:
RDATA, RDATAC, RREG, WREG, RRAM, WRAM 50 t
OSC
periods
t
6
CSREG, CSRAMX, CSRAM 200 t
OSC
periods
CSARAM, CSARAMX 1100 t
OSC
periods
t
7
SCLK edge to valid new D
OUT
50 ns
t
8
SCLK edge to D
OUT
, hold time 0 ns
Last SCLK edge to D
OUT
tri-state
t
9
6 10 t
OSC
periods
NOTE: D
OUT
goes tri-state immediately when CS goes HIGH.
t
10
CS LOW time after final SCLK edge 16 t
OSC
periods
Final SCLK edge of one op code until first edge SCLK of next command:
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, CSRAM,
4 t
OSC
periods
CSARAM, CSREG, SLEEP, RDATA, RDATAC, STOPC
CREG, CRAM 220 t
OSC
periods
t
11
CREGA 1600 t
OSC
periods
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL 7 DRDY periods
SELFCAL 14 DRDY periods
RESET (Command, SCLK or Pin), DSYNC 16 t
OSC
periods
8
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