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DEFINITIONS
ENOB +
−20 log
(
ppm
)
6.02
ǒ
2V
REF
PGA
Ǔ
10
ǒ
6.02ER
20
Ǔ
ǒ
V
REF
PGA
Ǔ
10
ǒ
6.02ER
20
Ǔ
f
DATA
+
ǒ
f
MOD
Decimation Ratio
Ǔ
+
ǒ
f
OSC
mfactor Decimation Ratio
Ǔ
f
SAMP
+
f
OSC
mfactor
f
SAMP
+
2f
OSC
mfactor
f
SAMP
+
8f
OSC
mfactor
f
SAMP
+
16f
OSC
mfactor
f
SAMP
+
16f
OSC
mfactor
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
Analog Input Voltage—the voltage at any one
The data from the A/D converter is output as codes,
analog input relative to AGND.
which then can be easily converted to other units,
Analog Input Differential Voltage—given by the such as ppm or volts. The equations and table below
following equation: (A
IN+
) – (A
IN–
). Thus, a positive show the relationship between bits or codes, ppm,
digital output is produced whenever the analog input and volts.
differential voltage is positive, while a negative digital
output is produced whenever the differential is
negative.
BITS rms BIPOLAR V
RMS
UNIPOLAR V
RMS
For example, when the converter is configured with a
2.5V reference and placed in a gain setting of 1, the
positive full-scale output is produced when the
analog input differential is 2.5V. The negative
full-scale output is produced when the differential is
24 298nV 149nV
–2.5V. In each case, the actual input voltages must
remain within the AGND to AV
DD
range.
22 1.19 µ V 597nV
20 4.77 µ V 2.39 µ V
Conversion Cycle—the term conversion cycle
18 19.1 µ V 9.55 µ V
usually refers to a discrete A/D conversion operation,
such as that performed by a successive
16 76.4 µ V 38.2 µ V
approximation converter. As used here, a conversion
14 505 µ V 152.7 µ V
cycle refers to the t
DATA
time period. However, each
12 1.22mV 610 µ V
digital output is actually based on the modulator
results from several t
DATA
time periods.
f
DATA
—the frequency of the digital output data
FILTER SETTING MODULATOR RESULTS
produced by the ADS1216. f
DATA
is also referred to
as the data rate.
Fast Settling 1 t
DATA
Time Period
Sinc
2
2 t
DATA
Time Period
Sinc
3
3 t
DATA
Time Period
f
MOD
—the frequency or speed at which the modulator
Data Rate—the rate at which conversions are
of the ADS1216 is running. This rate depends on the
completed. See definition for f
DATA
.
SPEED bit as shown below:
Decimation Ratio—defines the ratio between the
SPEED BIT f
MOD
output of the modulator and the output Data Rate.
0 f
OSC
/128
Valid values for the Decimation Ratio are from 20 to
2047. Larger Decimation Ratios will have lower
1 f
OSC
/256
noise.
f
OSC
—the frequency of the crystal input signal at the
Effective Resolution—the effective resolution of the
X
IN
input of the ADS1216.
ADS1216 in a particular configuration can be
expressed in two different units: bits rms (referenced
f
SAMP
—the frequency, or switching speed, of the
to output) and V
RMS
(referenced to input). Computed
input sampling capacitor. The value is given by one
directly from the converter output data, each is a
of the following equations:
statistical calculation. The conversion from one to the
PGA SETTING SAMPLING FREQUENCY
other is shown below.
1, 2, 4, 8
Effective number of bits (ENOB) or effective
resolution is commonly used to define the usable
resolution of the A/D converter. It is calculated from
8
empirical data taken directly from the device. It is
typically determined by applying a fixed known signal
16
source to the analog input and computing the
standard deviation of the data sample set. The rms
32
noise defines the ± σ interval about the sample mean.
64, 128
32
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