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DETAILED REGISTER DEFINITIONS

ADS1216

SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006

Table 3. Registers

ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00h SETUP ID ID ID SPEED REF EN REF HI BUF EN BIT ORDER

01h MUX PSEL3 PSEL2 PSEL1 PSEL0 NSEL3 NSEL2 NSEL1 NSEL0

02h ACR BOCS IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0 PGA2 PGA1 PGA0

03h IDAC1 IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0

04h IDAC2 IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC2_3 IDAC2_2 IDAC2_1 IDAC2_0

05h ODAC SIGN OSET_6 OSET_5 OSET_4 OSET_3 OSET_2 OSET_1 OSET_0

06h DIO DIO_7 DIO_6 DIO_5 DIO_4 DIO_3 DIO_2 DIO_1 DIO_0

07h DIR DIR_7 DIR_6 DIR_5 DIR_4 DIR_3 DIR_2 DIR_1 DIR_0

08h DEC0 DEC07 DEC06 DEC05 DEC04 DEC03 DEC02 DEC01 DEC00

09h M/DEC1 DRDY U/ B SMODE1 SMODE0 Reserved DEC10 DEC9 DEC8

0Ah OCR0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00

0Bh OCR1 OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR09 OCR08

0Ch OCR2 OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16

0Dh FSR0 FSR07 FSR06 FSR05 FSR04 FSR03 FSR02 FSR01 FSR00

0Eh FSR1 FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR09 FSR08

0Fh FSR2 FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16

SETUP (Address 00h) Setup Register

Reset value = iii01110.

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

ID ID ID SPEED REF EN REF HI BUF EN BIT ORDER

bits 7-5 Factory programmed bits

bit 4 SPEED: modulator clock speed

0 : f

MOD

= f

OSC

/128

1 : f

MOD

= f

OSC

/256

bit 3 REF EN: Internal voltage reference enable

0 = Internal voltage reference disabled

1 = Internal voltage reference enabled

bit 2 REF HI: internal reference voltage select

0 = Internal reference voltage = 1.25V

1 = Internal reference voltage = 2.5V

bit 1 BUF EN: buffer enable

0 = Buffer disabled

1 = Buffer enabled

bit 0 BIT ORDER: set order bits are transmitted

0 = Most significant bit transmitted first

1 = Least significant bit transmitted first data is always shifted into the part most significant bit first.

Data is always shifted out of the part most significant byte first. This configuration bit only controls the

bit order within the byte of data that is shifted out.

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