Datasheet

www.ti.com
Polarity (POL)
DATA READY
DSYNC OPERATION
MEMORY
Configuration
Registers
16bytes
SETUP
MUX
ACR
IDAC1
IDAC2
ODAC
DIO
DIR
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
RAM
128Bytes
Bank2
16bytes
Bank7
16bytes
Bank0
16bytes
REGISTER BANK
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
The serial clock polarity is specified by the POL
input. When SCLK is active high, set POL high.
When SCLK is active low, set POL low.
The DRDY output is used as a status signal to
indicate when data is ready to be read from the
ADS1216. DRDY goes low when new data is
available. It is reset high when a read operation from
the data register is complete. It also goes high prior
to the updating of the output register to indicate
when not to read from the device to ensure that a
data read is not attempted while the register is being
updated.
DSYNC is used to provide for synchronization of the
A/D conversion with an external event.
Synchronization can be achieved either through the
DSYNC pin or the DSYNC command. When the
DSYNC pin is used, the filter counter is reset on the
falling edge of DSYNC. The modulator is held in
reset until DSYNC is taken high. Synchronization
occurs on the next rising edge of the system clock
after DSYNC is taken high.
Two types of memory are used on the ADS1216:
registers and RAM. 16 registers directly control the
various functions (PGA, DAC value, Decimation
Ratio, etc.) and can be directly read or written to.
Collectively, the registers contain all the information
needed to configure the part, such as data format,
mux settings, calibration settings, decimation ratio,
etc. Additional registers, such as conversion data,
Figure 29. Memory Organization
are accessed through dedicated instructions.
The operation of the device is set up through
individual registers. The set of the 16 registers
required to configure the device is referred to as a
Register Bank, as shown in Figure 29 .
19
Submit Documentation Feedback