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SINC FILTERRESPONSE
3 (1)
( 3dB=0.262 f- ´
DATA
=15.76Hz)
Frequency(Hz)
0
-20
-40
-60
-80
-100
-120
0 30 12060 90 150 180 210 240 270 300
Gain(dB)
SINC FILTERRESPONSE
2 (1)
( 3dB=0.318 f- ´
DATA
=19.11Hz)
Frequency(Hz)
0
-20
-40
-60
-80
-100
-120
0 30 12060 90 150 180 210 240 270 300
Gain(dB)
FASTSETTLINGFILTERRESPONSE
(1)
( 3dB=0.469 f- ´
DATA
=28.125Hz)
Frequency(Hz)
0
-20
-40
-60
-80
-100
-120
0
NOTE:(1)f =60Hz.
DATA
30 12060 90 150 180 210 240 270 300
Gain(dB)
Chip Select ( CS)
DIGITAL I/O INTERFACE
Serial Clock (SCLK)
SERIAL PERIPHERAL INTERFACE (SPI)
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
Figure 28. Filter Frequency Responses
The chip select ( CS) input of the ADS1216 must be
The ADS1216 has eight pins dedicated for digital
externally asserted before a master device can
I/O. The default power-up condition for the digital I/O
exchange data with the ADS1216. CS must be low
pins are as inputs. All of the digital I/O pins are
for the duration of the transaction. CS can be tied
individually configurable as inputs or outputs. They
low.
are configured through the DIR control register. The
DIR register defines whether the pin is an input or
output, and the DIO register defines the state of the
digital output. When the digital I/O are configured as
SCLK, a Schmitt-Trigger input, clocks data transfer
inputs, DIO is used to read the state of the pin. If the
on the D
IN
input and D
OUT
output. When transferring
digital I/O are not used, either 1) configure as
data to or from the ADS1216, multiple bits of data
outputs; or 2) leave as inputs and tie to ground; this
may be transferred back-to-back with no delay in
configuration prevents excess power dissipation.
SCLKs or toggling of CS. Make sure to avoid glitches
on SCLK because they can cause extra shifting of
the data.
The SPI allows a controller to communicate
synchronously with the ADS1216. The ADS1216
operates in slave-only mode.
18
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