Datasheet

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PROGRAMMABLE GAIN AMPLIFIER (PGA) ON-CHIP VOLTAGE REFERENCE
PGA OFFSET DAC
V
RCAP
PIN
CLOCK GENERATOR
MODULATOR
C
1
Crystal
X
IN
X
OUT
C
2
VOLTAGE REFERENCE INPUT
ADS1216
SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, A selectable voltage reference (1.25V or 2.5V) is
or 128. Using the PGA can improve the effective available for supplying the voltage reference input.
resolution of the A/D converter. For instance, with a To use, connect V
REF–
to AGND and V
REF+
to
PGA of 1 on a 5V full-scale range, the A/D converter V
REFOUT
. The enabling and voltage selection are
can resolve to 1 µ V. With a PGA of 128 on a 40mV controlled through bits REF EN and REF HI in the
full-scale range, the A/D converter can resolve to Setup Register (see the Register Map section). The
75nV. 2.5V reference requires AV
DD
= +5V. When using the
on-chip voltage reference, the V
REFOUT
pin should be
bypassed with a 0.1 µ F capacitor to AGND.
The input to the PGA can be shifted by half the
full-scale input range of the PGA by using the ODAC
(Offset DAC) Register; see the Register Map section. This pin provides a bypass cap for noise filtering on
The ODAC register is an 8-bit value; the MSB is the internal V
REF
circuitry only. This pin is a sensitive pin;
sign and the seven LSBs provide the magnitude of therefore place the capacitor as close as possible
the offset. Using the ODAC does not reduce the and avoid any resistive loading. The recommended
performance of the A/D converter. See Application capacitor is a 1000pF ceramic cap. If an external
Report The Offset DAC (SBAA077 ), available for V
REF
is used, this pin can be left unconnected.
download at www.ti.com , for more information.
The clock source for the ADS1216 can be provided
The modulator is a single-loop, second-order system. from a crystal, oscillator, or external clock. When the
The modulator runs at a clock speed (f
MOD
) that is clock source is a crystal, external capacitors must be
derived from the external clock (f
OSC
), as shown in provided to ensure startup and a stable clock
Table 1 . The frequency division is determined by the frequency; this configuration is shown in Figure 26
SPEED bit in the Setup Register (see the Register and Table 2 .
Map section).
Table 1. Modulator Speed
SPEED BIT f
MOD
0 f
OSC
/128
1 f
OSC
/256
Figure 26. Crystal Connection
The ADS1216 uses a differential voltage reference
Table 2. Typical Clock Sources
input. The input signal is measured against the
differential voltage V
REF
≡ (V
REF+
) – (V
REF–
). For AV
DD
CLOCK
= +5V, V
REF
is typically +2.5V. For AV
DD
= +3V, V
REF
SOURCE FREQUENCY C
1
C
2
PART NUMBER
is typically +1.25V. As a result of the sampling nature
Crystal 2.4576 0–20pF 0–20pF ECS, ECSD 2.45 – 32
of the modulator, the reference input current
Crystal 4.9152 0–20pF 0–20pF ECS, ECSL 4.91
increases with higher modulator clock frequency
Crystal 4.9152 0–20pF 0–20pF ECS, ECSD 4.91
(f
MOD
) and higher PGA settings.
Crystal 4.9152 0–20pF 0–20pF CTS, MP 042 4M9182
16
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