Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 48

ADS1216

www.ti.com

FEATURES DESCRIPTION

APPLICATIONS

ADS1216

SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006

8-Channel, 24-Bit

ANALOG-TO-DIGITAL CONVERTER

• 24 BITS, NO MISSING CODES

The ADS1216 is a precision, wide dynamic range,

delta-sigma, Analog-to-Digital (A/D) converter with

• 0.0015% INL

24-bit resolution operating from 2.7V to 5.25V

• 22 BITS EFFECTIVE RESOLUTION

supplies. The delta-sigma A/D converter provides up

(PGA = 1), 19 BITS (PGA = 128)

to 24 bits of no-missing-code performance and an

• PGA FROM 1 TO 128

effective resolution of 22 bits.

• SINGLE-CYCLE SETTLING MODE

The eight input channels are multiplexed. Internal

• PROGRAMMABLE DATA OUTPUT RATES:

buffering can be selected to provide a very high input

up to 1kHz

impedance for direct connection to transducers or

low-level voltage signals. Burnout current sources

• ON-CHIP 1.25V/2.5V REFERENCE

are provided that allow for the detection of an open

• EXTERNAL DIFFERENTIAL REFERENCE:

or shorted sensor. An 8-bit Digital-to-Analog

0.1V to 2.5V

Converter (DAC) provides an offset correction with a

• ON-CHIP CALIBRATION

range of 50% of the FSR (Full-Scale Range).

• SPI™-COMPATIBLE

The PGA (Programmable Gain Amplifier) provides

selectable gains of 1 to 128 with an effective

• 2.7V TO 5.25V

resolution of 19 bits at a gain of 128. The A/D

• < 1mW POWER CONSUMPTION

conversion is accomplished with a second-order

delta-sigma modulator and programmable sinc filter.

The reference input is differential and can be used

• INDUSTRIAL PROCESS CONTROL

for ratiometric cancellation. The onboard current

• LIQUID/GAS CHROMATOGRAPHY

DACs operate independently with the maximum

current set by an external resistor.

• BLOOD ANALYSIS

• SMART TRANSMITTERS

The serial interface is SPI-compatible. Eight bits of

digital I/O are also provided that can be used for

• PORTABLE INSTRUMENTATION

input or output. The ADS1216 is designed for

• WEIGHT SCALES

high-resolution measurement applications in smart

• PRESSURE TRANSDUCERS

transmitters, industrial process control, weight

scales, chromatography, and portable

instrumentation.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI is a trademark of Motorola.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (40 pages)

PAGE 1
AD ADS1216 S1 216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES • • • • • • • • • • • • 24 BITS, NO MISSING CODES 0.0015% INL 22 BITS EFFECTIVE RESOLUTION (PGA = 1), 19 BITS (PGA = 128) PGA FROM 1 TO 128 SINGLE-CYCLE SETTLING MODE PROGRAMMABLE DATA OUTPUT RATES: up to 1kHz ON-CHIP 1.25V/2.5V REFERENCE EXTERNAL DIFFERENTIAL REFERENCE: 0.1V to 2.5V ON-CHIP CALIBRATION SPI™-COMPATIBLE 2.7V TO 5.
PAGE 2
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS: AVDD = +5V All specifications at TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to +5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. ADS1216 PARAMETER CONDITIONS MIN TYP Buffer OFF AGND – 0.1 Buffer ON AGND + 0.05 MAX UNIT AVDD + 0.1 V AVDD – 1.
PAGE 4
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS: AVDD = +5V (continued) All specifications at TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to +5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. ADS1216 PARAMETER CONDITIONS MIN REF HI = 1 2.4 TYP MAX UNIT 2.5 2.
PAGE 5
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS: AVDD = +3V All specifications at TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to +5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA = 10Hz, and VREF = +1.25V, unless otherwise specified. ADS1216 PARAMETER CONDITIONS MIN TYP Buffer OFF AGND – 0.1 Buffer ON AGND + 0.05 MAX UNIT AVDD + 0.1 V AVDD – 1.
PAGE 6
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS: AVDD = +3V (continued) All specifications at TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to +5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA = 10Hz, and VREF = +1.25V, unless otherwise specified. ADS1216 PARAMETER CONDITIONS MIN TYP MAX REF HI = 0 1.2 1.25 1.
PAGE 7
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 DIGITAL CHARACTERISTICS: TMIN to TMAX, DVDD +2.7V to +5.25V ADS1216 PARAMETER CONDITIONS MIN TYP MAX UNIT Digital input/output Logic family CMOS Logic level: VIH 0.8 × DVDD DVDD V Logic level: VIL DGND 0.2 × DVDD V Logic level: VOH IOH = 1mA DVDD – 0.
PAGE 8
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 TIMING CHARACTERISTICS CS t3 t1 t2 t10 SCLK (POL = 0) SCLK (POL = 1) t4 DIN MSB t2 t6 t5 t11 LSB (Command or Command and Data) t7 DOUT t8 MSB t9 (1) LSB (1) NOTE: (1) Bit Order = 0.
PAGE 9
ADS1216 www.ti.
PAGE 10
ADS1216 www.ti.
PAGE 11
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS At AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified.
PAGE 12
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS (continued) At AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. NOISE vs INPUT SIGNAL CMRR vs FREQUENCY 0.8 0.6 0.5 CMRR (dB) Noise (rms, ppm of FS) 0.7 0.4 0.3 0.2 0.1 0 -2.5 -1.5 0.5 -0.5 1.5 130 120 110 100 90 80 70 60 50 40 30 20 10 0 2.5 1 10 VIN (V) 100 Figure 7. 10k 100k Figure 8.
PAGE 13
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS (continued) At AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified.
PAGE 14
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS (continued) At AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified. OFFSET DAC – GAIN vs TEMPERATURE IDAC ROUT vs VOUT 1.00020 1.000 1.00016 +85°C 1.000 1.00008 IOUT (Normalized) Normalized Gain 1.00012 1.00004 1.00000 0.99996 0.99992 0.99988 +25°C 0.999 0.999 0.99984 -40°C 0.99980 0.99976 0.
PAGE 15
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 OVERVIEW INPUT MULTIPLEXER The input multiplexer provides for any combination of differential inputs to be selected on any of the input channels, as shown in Figure 25. If channel 1 is selected as the positive differential input channel, any other channel can be selected as the negative differential input channel. With this method, it is possible to have up to eight fully-differential input channels.
PAGE 16
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 PROGRAMMABLE GAIN AMPLIFIER (PGA) ON-CHIP VOLTAGE REFERENCE The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the effective resolution of the A/D converter. For instance, with a PGA of 1 on a 5V full-scale range, the A/D converter can resolve to 1µV. With a PGA of 128 on a 40mV full-scale range, the A/D converter can resolve to 75nV. A selectable voltage reference (1.25V or 2.
PAGE 17
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 CALIBRATION At the completion of calibration, the DRDY signal goes low, which indicates the calibration is finished and valid data is available. See Application Report Calibration Routine and Register Value Generation for the ADS121x Series (SBAA099), available for download at www.ti.com, for more information. The offset and gain errors in the ADS1216, or the complete system, can be reduced with calibration.
PAGE 18
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 3 (1) 2 (1) SINC FILTER RESPONSE (-3dB = 0.318 ´ fDATA = 19.11Hz) 0 0 -20 -20 -40 -40 Gain (dB) Gain (dB) SINC FILTER RESPONSE (-3dB = 0.262 ´ fDATA = 15.76Hz) -60 -60 -80 -80 -100 -100 -120 -120 0 30 60 90 120 150 180 210 240 270 300 0 30 60 90 Frequency (Hz) 120 150 180 210 240 270 300 Frequency (Hz) FAST SETTLING FILTER RESPONSE (-3dB = 0.469 ´ fDATA = 28.
PAGE 19
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 Polarity (POL) The serial clock polarity is specified by the POL input. When SCLK is active high, set POL high. When SCLK is active low, set POL low. Configuration Registers 16 bytes DATA READY SETUP MUX ACR IDAC1 IDAC2 ODAC DIO DIR DEC0 M/DEC1 OCR0 OCR1 OCR2 FSR0 FSR1 FSR2 The DRDY output is used as a status signal to indicate when data is ready to be read from the ADS1216. DRDY goes low when new data is available.
PAGE 20
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 RAM Reads and Writes to Registers and RAM occur on a byte basis. However, copies between registers and RAM occur on a bank basis. The RAM is independent of the Registers; for example, the RAM can be used as general-purpose RAM. The ADS1216 supports any combination of eight analog inputs. With this flexibility, the device can easily support eight unique configurations—one per input channel.
PAGE 21
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 REGISTER MAP Table 3.
PAGE 22
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 MUX (Address 01h) Multiplexer Control Register Reset value = 01h.
PAGE 23
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 IDAC1 (Address 03h) Current DAC 1 Reset value = 00h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0 The DAC code bits set the output of DAC1 from 0 to full-scale. The value of the full-scale current is set by this byte, VREF, RDAC, and the DAC1 range bits in the ACR register. IDAC2 (Address 04h) Current DAC 2 Reset value = 00h.
PAGE 24
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 DEC0 (Address 08h) Decimation Register (least significant 8 bits) Reset value = 80h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DEC07 DEC06 DEC05 DEC04 DEC03 DEC02 DEC01 DEC00 The decimation value is defined with 11 bits for a range of 20 to 2047. This register is the least significant eight bits. The three most significant bits are contained in the M/DEC1 register.
PAGE 25
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 OCR0 (Address 0Ah) Offset Calibration Coefficient (least significant byte) Reset value = 00h. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 OCR07 OCR06 OCR05 OCR04 OCR03 OCR02 OCR01 OCR00 OCR1 (Address 0Bh) Offset Calibration Coefficient (middle byte) Reset value = 00h.
PAGE 26
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 COMMAND DEFINITIONS The commands summarized in Table 4 control the operation of the ADS1216. All of the commands are stand-alone except for the register reads and writes (RREG, WREG) which require a second command byte plus data. Additional command and data bytes may be shifted in without delay after the first command byte.
PAGE 27
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 RDATA Read Data Description: Issue this command after DRDY goes low to read a single conversion result. After all 24 bits have been shifted out on DOUT, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY will then not return high until new data is being updated. See the Timing Characteristics for the required delay between the end of the RDATA command and the beginning of shifting data on DOUT: t6.
PAGE 28
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 STOPC Stop Read Data Continuous Description: Ends the continuous data output mode; refer to RDATAC in the Command Definitions section. The command must be issued after DRDY goes low and completed before DRDY goes high. DRDY DIN 000 1111 Figure 33. STOPC Command Sequence RREG Read from Registers Description: Output the data from up to 16 registers starting with the register address specified as part of the command.
PAGE 29
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 CREG Copy Registers to RAM Bank Description: This command copies the registers to the selected RAM bank. Do not issue additional commands while the copy operation is underway. 1st Command byte: 0100 0aaa where aaa is the RAM bank that will be updated with a copy of the registers. CREGA Copy Registers to All RAM Banks Description: This command copies the registers to all RAM banks.
PAGE 30
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 CSRAM Calculate Checksum for Selected RAM Bank Description: This command calculates the checksum for the selected RAM bank. The checksum is calculated as the sum of all the bytes in the registers with the carry ignored. Do not issue any additional commands while the checksum is being calculated.
PAGE 31
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 SYSGCAL System Gain Calibration Description: Performs a system gain calibration. The Full-Scale Calibration Register (FSC) is updated after this operation. DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready. Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete.
PAGE 32
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 DEFINITIONS Analog Input Voltage—the voltage at any one analog input relative to AGND. Analog Input Differential Voltage—given by the following equation: (AIN+) – (AIN–). Thus, a positive digital output is produced whenever the analog input differential voltage is positive, while a negative digital output is produced whenever the differential is negative. For example, when the converter is configured with a 2.
PAGE 33
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 Filter Selection—the ADS1216 uses a (sinx/x) filter or sinc filter. There are three different sinc filters that can be selected. A Fast-Settling filter will settle in one tDATA cycle. The Sinc2 filter will settle in two cycles and have lower noise. The Sinc3 will achieve lowest noise and higher number of effective bits, but requires three cycles to settle.
PAGE 34
ADS1216 www.ti.com SBAS171D – NOVEMBER 2000 – REVISED SEPTEMBER 2006 Changes from C Revision (May 2006) to D Revision ..................................................................................................... Page • • 34 Added title for Table 1......................................................................................................................................................... 16 Changed 11 registers to 16 registers in Description text of RREG section in Command Definitions.
PAGE 35
PACKAGE OPTION ADDENDUM www.ti.
PAGE 36
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1216Y/250 TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS1216Y/2K TQFP PFB 48 2000 330.0 16.4 9.6 9.6 1.5 12.0 16.
PAGE 37
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1216Y/250 TQFP PFB ADS1216Y/2K TQFP PFB 48 250 367.0 367.0 38.0 48 2000 367.0 367.0 38.
PAGE 38
MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
PAGE 39
PAGE 40
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.