Datasheet
ADS1212, 1213
34
SBAS064A
ADS1213U, P
A
IN
3N
A
IN
2P
A
IN
2N
A
IN
1P
A
IN
1N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
A
IN
3P
A
IN
4N
A
IN
4P
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
AV
DD
+5V
+5V
V
OL
0V
V
OL
+5V
R
1
49.9kΩ
C
2
6pF
C
1
6pF
DGND
XTAL
DGND
REF1004
+2.5V
0V
+5V
P1
2kΩ
1.0µF
+5V
ADS1213U, P
A
IN
3N
A
IN
2P
A
IN
2N
A
IN
1P
A
IN
1N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
A
IN
3P
A
IN
4N
A
IN
4P
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
1.0µF
AV
DD
+5V
+5V
+5V
0V
+5V
R
1
49.9kΩ
C
2
6pF
C
1
6pF
XTAL
DGND
DGND
REF1004
+2.5V
+5V
+5V
V
OH
V
OH
P1
2kΩ
DRDY A
DRDY B
DRDY C
DSYNC
t
DATA
t
DATA
t
DATA
t
DATA
voltage is 5V and the output format is Offset Binary
(FFFFFF
H
). For sink current, the worst-case condition oc-
curs when the analog input differential voltage is 0V and the
output format is Two’s Complement (000000
H
).
Note that SDOUT is tri-stated for the majority of the
conversion period and the opto-isolator connection must
take this into account.
Synchronization of Multiple Converters
The DSYNC input is used to synchronize the output data of
multiple ADS1212/13s. Synchronization involves configur-
ing each ADS1212/13 to the same Decimation Ratio and
Turbo Mode setting, and providing a common signal to the
X
IN
inputs. Then, the DSYNC signal is pulsed LOW (see
Figure 22 in the Timing section). This results in an internal
reset of the modulator count for the current conversion.
Thus, all the converters start counting from zero at the same
time, producing a DRDY LOW signal at approximately the
same point (see Figure 36).
FIGURE 36. Effect of Synchronization on Output Data
Timing.
FIGURE 35. Sink Current vs V
OL
for SDOUT Under Worst-Case Conditions.
30
25
20
15
10
5
0
SINK CURRENT
V
OL
(V)
012345
I
OUT
(mA)
25°C
85°C
–40°C
FIGURE 34. Source Current vs V
OH
for SDOUT Under Worst-Case Conditions.
30
25
20
15
10
5
0
SOURCE CURRENT
V
OH
(V)
021345
I
OUT
(mA)
25°C
85°C
–40°C
Note that an asynchronous DSYNC input may cause mul-
tiple converters to be different from one another by one X
IN
clock cycle. This should not be a concern for most applica-
tions. However, the Timing section contains information on
exactly synchronizing multiple converters to the same X
IN
clock cycle.