Datasheet

ADS1212, 1213
22
SBAS064A
t
4
t
5
t
6
t
8
t
7
t
9
SCLK
(Internal)
SDIO
(as input)
SDOUT
(or SDlO
as output)
Offset Calibration Register (OCR)
The OCR is a 24-bit register which contains the offset
correction factor that is applied to the conversion result before
it is placed in the Data Output Register (see Table XIII). In
most applications, the contents of this register will be the
result of either a self-calibration or a system calibration.
The OCR is both readable and writeable via the serial
interface. For applications requiring a more accurate offset
calibration, multiple calibrations can be performed, each
resulting OCR value read, the results averaged, and a more
precise offset calibration value written back to the OCR.
The actual OCR value will change from part-to-part and
with configuration, temperature, and power supply. Thus,
the actual OCR value for any arbitrary situation cannot be
accurately predicted. That is, a given system offset could not
be corrected simply by measuring the error externally, com-
puting a correction factor, and writing that value to the OCR.
In addition, be aware that the contents of the OCR are not
used to directly correct the conversion result. Rather, the
correction is a function of the OCR value. This function is
linear and two known points can be used as a basis for
interpolating intermediate values for the OCR. Consult the
Calibration section for more details.
Most Significant Bit
Byte 2
OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16
Byte 1
OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR9 OCR8
Byte 0
Least Significant Bit
OCR7 OCR6 OCR5 OCR4 OCR3 OCR2 OCR1 OCR0
TABLE XIII. Offset Calibration Register.
The contents of the OCR are in Two’s Complement format.
This is not affected by the DF bit in the Command Register.
Full-Scale Calibration Register (FCR)
The FCR is a 24-bit register which contains the full-scale
correction factor that is applied to the conversion result before
it is placed in the Data Output Register (see Table XIV). In
most applications, the contents of this register will be the
result of either a self-calibration or a system calibration.
TABLE XIV. Full-Scale Calibration Register.
Most Significant Bit
Byte 2
FSR23 FSR22 FSR21 FSR20 FSR19 FSR18 FSR17 FSR16
Byte 1
FSR15 FSR14 FSR13 FSR12 FSR11 FSR10 FSR9 FSR8
Byte 0
Least Significant Bit
FSR7 FSR6 FSR5 FSR4 FSR3 FSR2 FSR1 FSR0
The FCR is both readable and writable via the serial inter-
face. For applications requiring a more accurate full-scale
calibration, multiple calibrations can be performed, each
resulting FCR value read, the results averaged, and a more
precise calibration value written back to the FCR.
The actual FCR value will change from part-to-part and
with configuration, temperature, and power supply. Thus,
the actual FCR value for any arbitrary situation cannot be
accurately predicted. That is, a given system full-scale error
cannot be corrected simply by measuring the error exter-
nally, computing a correction factor, and writing that value
to the FCR. In addition, be aware that the contents of the
FCR are not used to directly correct the conversion result.
Rather, the correction is a function of the FCR value. This
function is linear and two known points can be used as a
basis for interpolating intermediate values for the FCR.
Consult the Calibration section for more details. The con-
tents of the FCR are in unsigned binary format. This is not
affected by the DF bit in the Command Register.
TIMING
Table XV and Figures 13 through 21 define the basic digital
timing characteristics of the ADS1212/13. Figure 13 and the
associated timing symbols apply to the X
IN
input signal.
Figures 14 through 20 and associated timing symbols apply
to the serial interface signals (SCLK, SDIO, SDOUT, and
CS) and their relationship to DRDY. The serial interface is
discussed in detail in the Serial Interface section. Figure 21
and the associated timing symbols apply to the maximum
DRDY rise and fall times.
FIGURE 13. X
IN
Clock Timing.
t
XIN
t
2
X
IN
t
3
FIGURE 14. Serial Input/Output Timing, Master Mode.
FIGURE 15. Serial Input/Output Timing, Slave Mode.
t
10
t
11
t
12
t
14
t
13
t
15
SCLK
(External)
SDIO
(as input)
SDOUT
(or SDlO
as output)