Datasheet
ADS1212, 1213
21
SBAS064A
Table XI. Decimation Ratios for Various Data Rates (Turbo Mode Rate of 1 and 1MHz clock).
CH1 CH0 ACTIVE INPUT
0 0 Channel 1 Default
0 1 Channel 2
1 0 Channel 3
1 1 Channel 4
TURBO AVAILABLE
MODE PGA
SF2 SF1 SF0 RATE SETTINGS
00011, 2, 4, 8, 16Default
00121, 2, 4, 8
0104 1, 2, 4
0118 1, 2
10016 1
Most Significant Bit
Byte 2
DOR23 DOR22 DOR21 DOR20 DOR19 DOR18 DOR17 DOR16
Byte 1
DOR15 DOR14 DOR13 DOR12 DOR11 DOR10 DOR9 DOR8
Byte 0
Least Significant Bit
DOR7 DOR6 DOR5 DOR4 DOR3 DOR2 DOR1 DOR0
TABLE XII. Data Output Register.
G2-G0 (PGA Control) Bits—The G2-G0 bits control the
gain setting of the PGA, as follows:
GAIN AVAILABLE TURBO
G2 G1 G0 SETTING MODE RATES
0 0 0 1 1, 2, 4, 8, 16 Default
0 0 1 2 1, 2, 4, 8
0 1 0 4 1, 2, 4
011 8 1, 2
100 16 1
The gain is partially implemented by increasing the input
capacitor sampling frequency, which is given by the follow-
ing equation:
f
SAMP
= G • TMR • f
XIN
/128
where G is the gain setting and TMR is the Turbo Mode
Rate. The product of G and TMR cannot exceed 16. The
sampling frequency of the input capacitor directly relates to
the analog input impedance. See the Programmable Gain
Amplifier and Analog Input sections for more details.
CH1-CH0 (Channel Selection) Bits—The CH1 and CH0 bits
control the input multiplexer on the ADS1213, as follows:
(For the ADS1212, CH1 and CH0 must always be zero.) The
channel change takes effect when the last bit of byte 2 has
been written to the Command Register. Output data will not
be valid for the next three conversions despite the DRDY
signal indicating that data is ready. On the fourth time that
DRDY goes LOW after a channel change has been written
to the Command Register, valid data will be present in the
Data Output Register (see Figure 4).
SF2-SF0 (Turbo Mode Rate) Bits—The SF2-SF0 bits
control the input capacitor sampling frequency and modula-
tor rate, as follows:
The input capacitor sampling frequency and modulator rate
can be calculated from the following equations:
f
SAMP
= G • TMR • f
XIN
/128
f
MOD
= TMR • f
XIN
/128
where G is the gain setting and TMR is the Turbo Mode
Rate. The sampling frequency of the input capacitor directly
relates to the analog input impedance. The modulator rate
relates to the power consumption of the ADS1212/13 and
the output data rate. See the Turbo Mode, Analog Input, and
Reference Input sections for more details.
DR12-DR0 (Decimation Ratio) Bits—The DR12-DR0 bits
control the decimation ratio of the ADS1212/13. In essence,
these bits set the number of modulator results which are used in
the digital filter to compute each individual conversion result.
Since the modulator rate depends on both the ADS1212/13
clock frequency and the Turbo Mode Rate, the actual output
data rate is given by the following equation:
f
DATA
= f
XIN
• TMR/(128 • (Decimation Ratio + 1))
where TMR is the Turbo Mode Rate. Table XI shows
various data rates and corresponding decimation ratios (with
a 1MHz clock). Valid decimation ratios are from 19 to 8000.
Outside of this range, the digital filter will compute results
incorrectly due to inadequate or too much data.
Data Output Register (DOR)
The DOR is a 24-bit register which contains the most recent
conversion result (see Table XII). This register is updated
with a new result just prior to DRDY going LOW. If the
contents of the DOR are not read within a period of time
defined by 1/f
DATA
–24•(1/f
XIN
), then a new conversion
result will overwrite the old. (DRDY is forced HIGH prior
to the DOR update, unless a read is in progress).
The contents of the DOR can be in Two’s Complement or
Offset Binary format. This is controlled by the DF bit of the
Command Register. In addition, the contents can be limited to
unipolar data only with the U/B bit of the Command Register.
DATA DECI-
RATE MATION
(HZ) RATIO DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
391190000000010011
250300000000011110
100770000001001101
601290000010000001
501550000010011011
203900000110000110
107800001100001100
0.96 8000 1 1 1 1 1 0 1 0 0 0 0 0 0