Datasheet

ADS1210, ADS1211
4
SBAS034B
www.ti.com
PGA
+2.5V
Reference
+3.3V Bias
Generator
Clock Generator
Serial Interface
Second-Order
∆Σ
Modulator
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
Third-Order
Digital Filter
Micro Controller
Modulator Control
11
9
10
12
13
AGND AV
DD
REF
OUT
REF
IN
V
BIAS
X
IN
X
OUT
3
1
2
16 17 18 4 7 8
65 1415
DSYNC CS DRDYMODE
A
IN
P
A
IN
N
SCLK
DGND
DV
DD
SDIO
SDOUT
ADS1210
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
A
IN
P
A
IN
N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
ADS1210 SIMPLIFIED BLOCK DIAGRAM
ADS1210 PIN DEFINITIONS
PIN NO NAME DESCRIPTION
1A
IN
P Noninverting Input.
2A
IN
N Inverting Input.
3 AGND Analog Ground.
4V
BIAS
Bias Voltage Output, +3.3V nominal.
5 CS Chip Select Input.
6 DSYNC Control Input to Synchronize Serial Output Data.
7X
IN
System Clock Input.
8X
OUT
System Clock Output (for Crystal or Resonator).
9 DGND Digital Ground.
10 DV
DD
Digital Supply, +5V nominal.
11 SCLK Clock Input/Output for serial data transfer.
12 SDIO Serial Data Input (can also function as Serial Data
Output).
13 SDOUT Serial Data Output.
14 DRDY Data Ready.
15 MODE SCLK Control Input (Master = 1, Slave = 0).
16 AV
DD
Analog Supply, +5V nominal.
17 REF
OUT
Reference Output, +2.5V nominal.
18 REF
IN
Reference Input.
TOP VIEW DIP/SOIC
ADS1210 PIN CONFIGURATION