Datasheet

ADS1210, ADS1211
23
SBAS034B
www.ti.com
TABLE XV. Digital Timing Characteristics.
SYMBOL DESCRIPTION MIN NOM MAX UNITS
f
XIN
X
IN
Clock Frequency 0.5 10 MHz
t
XIN
X
IN
Clock Period 100 2000 ns
t
2
X
IN
Clock High 0.4 • t
XIN
ns
t
3
X
IN
Clock LOW 0.4 • t
XIN
ns
t
4
Internal Serial Clock HIGH t
XIN
ns
t
5
Internal Serial Clock LOW t
XIN
ns
t
6
Data In Valid to Internal SCLK Falling Edge (Setup) 40 ns
t
7
Internal SCLK Falling Edge to Data In Not Valid (Hold) 20 ns
t
8
Data Out Valid to Internal SCLK Falling Edge (Setup) t
XIN
–25 ns
t
9
Internal SCLK Falling Edge to Data Out Not Valid (Hold) t
XIN
ns
t
10
External Serial Clock HIGH 2.5 • t
XIN
ns
t
11
External Serial Clock LOW 2.5 • t
XIN
ns
t
12
Data In Valid to External SCLK Falling Edge (Setup) 40 ns
t
13
External SCLK Falling Edge to Data In Not Valid (Hold) 20 ns
t
14
Data Out Valid to External SCLK Falling Edge (Setup) t
XIN
–40 ns
t
15
External SCLK Falling Edge to Data Out Not Valid (Hold) 1.5 • t
XIN
ns
t
16
Falling Edge of DRDY to First SCLK Rising Edge 6 • t
XIN
ns
(Master Mode, CS Tied LOW)
t
17
Falling Edge of Last SCLK for INSR to Rising Edge of First 5 • t
XIN
ns
SCLK for Register Data (Master Mode)
t
18
Falling Edge of Last SCLK for Register Data to Rising Edge 3 • t
XIN
ns
of DRDY (Master Mode)
t
19
Falling Edge of Last SCLK for INSR to Rising Edge of First 5.5 • t
XIN
ns
SCLK for Register Data (Slave Mode) ns
t
20
Falling Edge of Last SCLK for Register Data to Rising Edge 4 • t
XIN
5 • t
XIN
ns
of DRDY (Slave Mode)
t
21
Falling Edge of DRDY to Falling Edge of CS (Master and 0.5 • t
XIN
ns
Slave Mode)
t
22
Falling Edge of CS to Rising Edge of SCLK (Master Mode) 5 • t
XIN
6 • t
XIN
ns
t
23
Rising Edge of DRDY to Rising Edge of CS (Master and 10 ns
Slave Mode)
t
24
Falling Edge of CS to Rising Edge of SCLK (Slave Mode) 5.5 • t
XIN
ns
t
25
Falling Edge of Last SCLK for INSR to SDIO Tri-state 2 • t
XIN
ns
(Master Mode)
t
26
SDIO as Output to Rising Edge of First SCLK for Register 2 • t
XIN
ns
Data (Master and Slave Modes)
t
27
Falling Edge of Last SCLK for INSR to SDIO Tri-state 3 • t
XIN
4 • t
XIN
ns
(Slave Mode)
t
28
SDIO Tri-state Time (Master and Slave Modes) t
XIN
ns
t
29
Falling Edge of Last SCLK for Register Data to SDIO Tri-State t
XIN
ns
(Master Mode)
t
30
Falling Edge of Last SCLK for Register Data to SDIO 2 • t
XIN
3 • t
XIN
ns
Tri-state (Slave Mode)
t
31
DRDY Fall Time 30 ns
t
32
DRDY Rise Time 30 ns
t
33
Minimum DSYNC LOW Time 10.5 • t
XIN
ns
t
34
DSYNC Valid HIGH to Falling Edge of X
IN
(for Exact 10 ns
Synchronization of Multiple Converters only)
t
35
Falling Edge of X
IN
to DSYNC Not Valid LOW (for Exact 10 ns
Synchronization of Multiple Converters only)
t
36
Falling Edge of Last SCLK for Register Data to Rising Edge 20.5 • t
XIN
ns
of First SCLK of next INSR (Slave Mode, CS Tied LOW)
t
37
Rising Edge of CS to Falling Edge of CS (Slave Mode, 10.5 • t
XIN
ns
Using CS)
t
38
Falling Edge of DRDY to First SCLK 5.5 • t
XIN
ns
Rising Edge (Slave Mode, CS Tied LOW)