Datasheet

0
-10
-20
-30
-40
-50
-60
-70
-80
Gain(dB)
Frequency(kHz)
0 200 400 600 800 1000 1200 1400 1600
OSR=32
f =10MHz/32=312.5kHz
3dB:81.9kHz
DATA
-
H(z)=
1 z-
-OSR
1 z-
-1
3
0
10
20
30
40
50
60
-
-
-
-
-
-
Gain(dB)
100
100k
Frequency(Hz)
10k1k
ADS1209
www.ti.com SBAS491 –FEBRUARY 2010
DIGITAL INTERFACE
This behavior can be adjusted by a cascaded filter
INTRODUCTION
structure. For example, the first decimation stage can
be a Sinc
3
filter with a low OSR, and the second
The analog signal connected to the input of the ΔΣ
stage a high-order filter.
modulator is converted using the clock signal applied
to the modulator. The result of the conversion (or
For more information, see application note SBAA094,
modulation) is available on one of the OUTx pins,
Combining the ADS1202 with an FPGA Digital Filter
depending on the modulator. In addition, a common
for Current Measurement in Motor Control
clock output signal (CLKOUT) for both
Applications, available for download at www.ti.com.
simultaneously-sampling modulators is provided. If
CLKSEL = 1, CLKIN must not be left floating, but
should tied to BVDD or BGND.
MODES OF OPERATION
The device clock of the ADS1209 is 20MHz by
default. The device clock can either be generated by
the internal 20MHz RC oscillator or can be provided
by an external clock source. For this purpose, the
CLKIN pin is provided; it is controlled by the mode
setting, CLKSEL.
The device clock is divided by two before being used
as the modulator clock. Therefore, the default clock
frequency of the modulator is 10MHz. With a possible
external clock range of 1MHz to 24MHz, the
modulator operates between 500kHz and 12MHz.
Figure 25. Frequency Response of Sinc
3
Filter
(OSR = 32)
FILTER USAGE
The modulator generates a bitstream. In order to
output a digital word equivalent to the analog input
voltage, the bitstream must be processed by a digital
filter.
A simple filter, built with minimal effort and hardware,
is the Sinc
3
filter shown in Equation 2:
(2)
This filter provides the best output performance with a
relatively low number of gates required for
implementation. For oversampling ratios in the range
of 16 to 256, this filter architecture represents a good
choice. All the characterizations in this data sheet are
done using a Sinc
3
filter with an oversampling ratio of
Figure 26. Frequency Response of Sinc
3
Filter
OSR = 256 and an output word width of 16 bits.
(OSR = 256)
In a Sinc
3
filter response (shown in Figure 25 and
Figure 26), the location of the first notch occurs at the
frequency of output data rate f
DATA
= f
MOD
/OSR. The
–3dB point is located at half the Nyquist frequency or
f
DATA
/4.
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