Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External TSSOP 24

2nd-Order

DS Modulator

CHA+

AVDD

CHA-

Output

Interface

Circuit

Oscillator

20MHz

Out EN

Clock

Select

Divider

REFINA

Reference

Voltage

2.5V

REFOUT

OUTA

OUTB

CLKIN

AGND BGND

BVDD

CLKOUT

CLKSEL

2nd-Order

DS Modulator

CHB+

CHB-

REFINB

ADS1209

www.ti.com

SBAS491 –FEBRUARY 2010

Two 1-Bit, 10MHz, 2nd-Order

Delta-Sigma Modulators

Check for Samples: ADS1209

FEATURES

DESCRIPTION

• 16-Bit Resolution

The ADS1209 is a two-channel, high-performance,

delta-sigma (ΔΣ) modulator with an 86dB dynamic

• 13-Bit Linearity

range, operating from a single +5V supply. The

• ±2.3V Specified Input Voltage Range

differential inputs are ideal for direct connection to

• Internal Reference Voltage: 2%

signal sources in an industrial environment. With the

• Gain Error: 0.5% appropriate digital filter and modulator rate, the

device can be used to achieve 16-bit analog-to-digital

• Two Independent Delta-Sigma Modulators

(A/D) conversion with no missing codes. Effective

• Two Input Reference Buffers

accuracy of 14 bits can be obtained with a digital filter

• On-Chip Oscillator

bandwidth of 20kHz at a modulator rate of 10MHz.

The ADS1209 is designed for use in high-resolution

• Selectable Internal or External Clock

measurement applications including current

• Specified Temperature Range:

measurements, industrial process control, and

–40°C to +105°C

resolvers. It is available in a TSSOP-24 package and

• TSSOP-24 Package

is specified for operation over the ambient

temperature range of –40°C to +105°C.

APPLICATIONS

• Motor Control

• Current Measurement

• Resolver

• Industrial Process Control

• Instrumentation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (23 pages)

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ADS1209 www.ti.com SBAS491 – FEBRUARY 2010 Two 1-Bit, 10MHz, 2nd-Order Delta-Sigma Modulators Check for Samples: ADS1209 FEATURES DESCRIPTION • • • • • • • • • • The ADS1209 is a two-channel, high-performance, delta-sigma (ΔΣ) modulator with an 86dB dynamic range, operating from a single +5V supply. The differential inputs are ideal for direct connection to signal sources in an industrial environment.
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ADS1209 SBAS491 – FEBRUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS1209 www.ti.com SBAS491 – FEBRUARY 2010 RECOMMENDED OPERATING CONDITIONS PARAMETER MIN NOM MAX UNIT 4.5 5 5.5 V Low-voltage levels 2.7 3.0 3.6 V 5V logic levels 4.5 5 5.5 V 0.5 2.5 2.6 V 0 AVDD V –0.92 × VREF +0.
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ADS1209 SBAS491 – FEBRUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over operating ambient temperature range of –40°C to +105°C, AVDD = 5V, BVDD = 3V, CHx+ = 0.2V to 4.8V, CHx– = 2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKIN = 20MHz, and 16-bit Sinc3 filter with OSR = 256, unless otherwise noted. ADS1209 PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT 8 10 12 MHz 7.
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ADS1209 www.ti.com SBAS491 – FEBRUARY 2010 ELECTRICAL CHARACTERISTICS (continued) Over operating ambient temperature range of –40°C to +105°C, AVDD = 5V, BVDD = 3V, CHx+ = 0.2V to 4.8V, CHx– = 2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKIN = 20MHz, and 16-bit Sinc3 filter with OSR = 256, unless otherwise noted. ADS1209 PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT DIGITAL INPUTS Logic family LVCMOS VIH High-level input voltage BVDD = 3.6V 2 BVDD + 0.
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ADS1209 SBAS491 – FEBRUARY 2010 www.ti.com PIN CONFIGURATION PW PACKAGE TSSOP-24 (TOP VIEW) AVDD 1 24 AVDD AGND 2 23 REFOUT REFINA 3 22 AGND NC 4 21 OUTA CHA+ 5 20 OUTB CHA- 6 19 CLKOUT ADS1209 CHB- 7 18 BGND CHB+ 8 17 BVDD NC 9 16 CLKIN REFINB 10 15 CLKSEL AGND 11 14 AGND AVDD 12 13 AVDD PIN DESCRIPTIONS PIN NO. I/O (1) AVDD 1 P Analog power supply; nominal 5V. Decouple to AGND with a 0.1µF ceramic capacitor. AGND 2 P Analog ground.
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ADS1209 www.ti.com SBAS491 – FEBRUARY 2010 PARAMETER MEASUREMENT INFORMATION t2 t1 CLKIN tD1 t3 tD2 t4 CLKOUT tD3 tH1 OUTx Figure 1. ADS1209 Timing Diagram TIMING CHARACTERISTICS (1) Over the recommended operating ambient temperature range of –40°C to +105°C, AVDD = 5V, and BVDD = 2.7V to 5V, unless otherwise noted. MIN MAX UNIT t1 CLKIN period PARAMETER CLKSEL = 0 TEST CONDITIONS 41.
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ADS1209 SBAS491 – FEBRUARY 2010 www.ti.com TYPICAL CHARACTERISTICS At AVDD = 5V, BVDD = 3V, CHx+ = +0.2V to +4.8V, CHx– = +2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKSEL = 1, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. INTEGRAL NONLINEARITY MATCH vs INPUT SIGNAL 8 4 6 3 4 2 INL Match (LSB) INL (LSB) INTEGRAL NONLINEARITY vs INPUT SIGNAL VOLTAGE 2 0 -2 -40°C +25°C +85°C +105°C -4 -6 -8 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 Differential Input Voltage (V) 2.
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ADS1209 www.ti.com SBAS491 – FEBRUARY 2010 TYPICAL CHARACTERISTICS (continued) At AVDD = 5V, BVDD = 3V, CHx+ = +0.2V to +4.8V, CHx– = +2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKSEL = 1, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted. POWER-SUPPLY REJECTION RATIO vs RIPPLE FREQUENCY COMMON-MODE REJECTION RATIO vs INPUT SIGNAL FREQUENCY 90 120 CMRR (dB) 130 PSRR (dB) 100 80 70 110 100 60 90 100 1k 100 10k 1k 10k Figure 8. Figure 9.
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ADS1209 SBAS491 – FEBRUARY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At AVDD = 5V, BVDD = 3V, CHx+ = +0.2V to +4.8V, CHx– = +2.5V, VREFIN = VREFOUT = 2.5V (internal), CLKSEL = 1, and 16-bit Sinc3 filter, with OSR = 256, unless otherwise noted.
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ADS1209 www.ti.com SBAS491 – FEBRUARY 2010 GENERAL DESCRIPTION The ADS1209 is a two-channel, second-order, CMOS device with two delta-sigma (ΔΣ) modulators, designed for medium- to high-resolution A/D signal conversions from dc to 40kHz (filter response –3dB) if an oversampling ratio (OSR) of 64 is chosen. The output of the converter (OUTx) provides a stream of digital ones and zeros. The time average of this serial output is proportional to the analog input voltage.
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ADS1209 SBAS491 – FEBRUARY 2010 www.ti.com AVDD +5V BVDD 27W R1 CH A+ OPA4354 IN+ CH A- 0.1nF 2nd-Order DS Modulator R2 OUT A Output Interface Circuit OUT B FPGA or ASIC REFIN A CLKOUT +5V CH B+ 27W R1 OPA4354 CH B- 2nd-Order DS Modulator +3V BVDD 0.1mF BGND INREFIN B R2 Divider +5V +3V 27W R1 Clock Select OPA4354 IN+ CLKIN CLKSEL 0.1nF +5V R2 AVDD +5V Out EN +5V RC Oscillator 20MHz 27W R1 OPA4354 IN- REFOUT R2 Reference Voltage 2.5V 0.1mF AVDD +5V AVDD +5V 0.
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ADS1209 www.ti.com SBAS491 – FEBRUARY 2010 THEORY OF OPERATION The differential analog input of the ADS1209 is implemented with a switched-capacitor circuit. This circuit implements a second-order modulator stage, which digitizes the analog input signal into a 1-bit output stream. The clock source can be internal as well as external. Every analog input signal is continuously sampled by the modulator and compared to a reference voltage that is applied to the REFINx pin.
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ADS1209 SBAS491 – FEBRUARY 2010 www.ti.com Modulator The ADS1209 can be operated in two modes. When CKLSEL = 1, the two modulators operate using the internal clock, which is fixed at 20MHz. When CKLSEL = 0, the modulators operate using an external clock. In both modes, the clock is internally divided by two and functions as the modulator clock. The frequency of the external clock can vary from 1MHz to 24MHz to adjust for the clock requirements of the application.
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ADS1209 www.ti.com SBAS491 – FEBRUARY 2010 DIGITAL INTERFACE INTRODUCTION The analog signal connected to the input of the ΔΣ modulator is converted using the clock signal applied to the modulator. The result of the conversion (or modulation) is available on one of the OUTx pins, depending on the modulator. In addition, a common clock output signal (CLKOUT) for both simultaneously-sampling modulators is provided. If CLKSEL = 1, CLKIN must not be left floating, but should tied to BVDD or BGND.
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ADS1209 SBAS491 – FEBRUARY 2010 www.ti.com The effective number of bits (ENOB) can be used to compare the performance of A/D converters and ΔΣ modulators. Figure 27 shows the ENOB of the ADS1209 with different filter types. In this data sheet, the ENOB is calculated from the SNR as shown in Equation 3: SNR = 1.76dB + 6.02dB ´ ENOB (3) the modulator clock divided by the OSR. For overcurrent protection, filter types other than Sinc3 may be a better choice. A simple example is a Sinc2 filter.
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ADS1209 www.ti.com SBAS491 – FEBRUARY 2010 LAYOUT CONSIDERATIONS POWER SUPPLIES DECOUPLING An applied external digital filter rejects high-frequency noise. PSRR and CMRR improve at higher frequencies because the digital filter suppresses high-frequency noise. However, the suppression of the filter is not infinite while high-frequency noise continues to influence the conversion result. Good decoupling practices must be used for the ADS1209 and for all components in the design.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS1209SPWR Package Package Pins Type Drawing TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1209SPWR TSSOP PW 24 2000 367.0 367.0 38.
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