Datasheet

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SBAS312B − JANUARY 2005 − REVISED AUGUST 2007
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7
PARAMETER MEASUREMENT INFORMATION
CLKOUT
OUT x
t
C1
t
W2
t
D4
t
D3
t
C2
t
W1
t
D1
t
D2
CLKIN
Figure 1. ADS1205 Timing Diagram
TIMING REQUIREMENTS
(1)
over recommended operating free-air temperature range at −40°C to +85°C, AV
DD
= 5V, and BV
DD
= 2.7 to 5V, unless otherwise noted.
PARAMETER MIN MAX UNIT
t
C1
CLKIN period: (CLKSEL = 0) 41.6
(2)
1000 ns
t
W1
CLKIN high time: (CLKSEL = 0) 10 t
C1
− 10 ns
t
C2
CLKOUT period using internal oscillator (CLKSEL = 1) 83 125 ns
CLKOUT period using external clock (CLKSEL = 0) 2 × t
C1
ns
t
W2
CLKOUT high time (t
C2
/2) − 5 (t
C2
/2) + 5 ns
t
D1
CLKOUT rising edge delay after CLKIN rising edge: (CLKOUT = 0) 0 10 ns
t
D2
CLKOUT falling edge delay after CLKIN rising edge: (CLKOUT = 0) 0 10 ns
t
D3
Data valid delay after rising edge of CLKOUT (CLKSEL = 1) (t
C2
/4) − 8 (t
C2
/4) + 8 ns
t
D4
Data valid delay after rising edge of CLKOUT (CLKSEL = 0) t
W1
− 3 t
W1
+ 7 ns
(1)
All input signals are specified with t
R
= t
F
= 5ns (10% to 90% of BV
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 1.
(2)
With reduced accuracy, the minimum clock period can go down to 30ns.