Datasheet

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SBAS312B − JANUARY 2005 − REVISED AUGUST 2007
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16
V
REF
X
4
X
6
Integrator 2
Comparator
f
CLK
DATA
D/A Converter
X
3
X
2
X(t)
f
S
Integrator 1
Figure 31. Block Diagram of the 2nd-Order Modulator
DIGITAL OUTPUT
A differential input signal of 0V will ideally produce a
stream of ones and zeros that are high 50% of the time and
low 50% of the time. A differential input of +2V produces
a stream of ones and zeros that are high 80% of the time.
A differential input of –2V produces a stream of ones and
zeros that are high 20% of the time. The input voltage
versus the output modulator signal is shown in Figure 32.
DIGITAL INTERFACE
INTRODUCTION
The analog signal connected to the input of the
delta-sigma modulator is converted using the clock signal
applied to the modulator. The result of the conversion, or
modulation, is generated and sent to the OUTx pin from the
delta-sigma modulator. In most applications where a direct
connection is realized between the delta-sigma modulator
and an ASIC or FPGA (each with an implemented filter),
the two standard signals per modulator (CLKOUT and
OUTx) are provided from the modulator. The output clock
signal is equal for both modulators. If CLKSEL = 1, CLKIN
must always be set either high or low.
MODES OF OPERATION
The system clock of the ADS1205 is 20MHz by default.
The system clock can be provided either from the internal
20MHz RC oscillator or from an external clock source. For
this purpose, the CLKIN pin is provided; it is controlled by
the mode setting, CLKSEL.
The system clock is divided by two for the modulator clock.
Therefore, the default clock frequency of the modulator is
10MHz. With a possible external clock range of 1MHz to
33MHz, the modulator operates between 500kHz and
16.5MHz.
Modulator Output
Analog Input
+FS (Analog Input)
−
FS (Analog Input)
Figure 32. Analog Input vs Modulator Output of the ADS1205