Datasheet

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SBAS312B − JANUARY 2005 − REVISED AUGUST 2007
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15
THEORY OF OPERATION
The differential analog input of the ADS1205 is
implemented with a switched-capacitor circuit. This circuit
implements a 2nd-order modulator stage, which digitizes
the analog input signal into a 1-bit output stream. The clock
source can be internal as well as external. Different
frequencies for this clock allow for a variety of solutions
and signal bandwidths. Every analog input signal is
continuously sampled by the modulator and compared to
a reference voltage that is applied to the REFINx pin. A
digital stream, which accurately represents the analog
input voltage over time, appears at the output of the
corresponding converter.
ANALOG INPUT STAGE
Analog Input
The topology of the analog inputs of ADS1205 is based on
a fully differential switched-capacitor architecture. This
input stage provides the mechanism to achieve low
system noise, high common-mode rejection (108dB), and
excellent power-supply rejection.
The input impedance of the analog input is dependent on
the modulator clock frequency (f
CLK
), which is also the
sampling frequency of the modulator. Figure 30 shows the
basic input structure of one channel of the ADS1205. The
relationship between the input impedance of the ADS1205
and the modulator clock frequency is:
Z
IN
+
100kW
f
MOD
ń10MHz
The input impedance becomes a consideration in designs
where the source impedance of the input signal is high.
This high impedance may cause degradation in gain,
linearity, and THD. The importance of this effect depends
on the desired system performance. There are two
restrictions on the analog input signals, CH x+ and CH x−.
If the input voltage exceeds the range (GND – 0.3V) to
(V
DD
+ 0.3V), the input current must be limited to 10mA
because the input protection diodes on the front end of the
converter will begin to turn on. In addition, the linearity and
the noise performance of the device are ensured only
when the differential analog voltage resides within ±2V
(with V
REF
as a midpoint); however, the FSR input voltage
is ±2.5V.
Modulator
The ADS1205 can be operated in two modes. When
CKLSEL = 1, the two modulators operate using the internal
clock, which is fixed at 20MHz. When CKLSEL = 0, the
modulators operate using an external clock. In both modes,
the clock is divided by two internally and functions as the
modulator clock. The frequency of the external clock can vary
from 1MHz to 33MHz to adjust for the clock requirements of
the application.
The modulator topology is fundamentally a 2nd-order,
switched-capacitor, delta-sigma modulator, such as the one
conceptualized in Figure 31. The analog input voltage and
the output of the 1-bit digital-to-analog converter (DAC) are
differentiated, providing analog voltages at X2 and X3. The
voltages at X2 and X3 are presented to their individual
integrators. The output of these integrators progresses in a
negative or positive direction. When the value of the signal
at X4 equals the comparator reference voltage, the output of
the comparator switches from negative to positive, or positive
to negative, depending on its original state. When the output
value of the comparator switches from high to low or vice
versa, the 1-bit DAC responds on the next clock pulse by
changing its analog output voltage at X6, causing the
integrators to progress in the opposite direction. The
feedback of the modulator to the front end of the integrators
forces the value of the integrator output to track the average
of the input.
650
Ω
650
Ω
Switching Frequency = CLK
High
Impedance
>1G
Ω
1.2pF
V
CM
A
IN
+
High
Impedance
>1G
Ω
1.2pF
0.4pF
0.4pF
A
IN
−
Figure 30. Input Impedance of the ADS1205
(1)