SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 FEATURES D 16-Bit Resolution D 14-Bit Linearity D ±2.5V Input Range at 2.5V D Internal Reference Voltage: 2% D Gain Error: 0.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at −40°C to +85°C, AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted. PARAMETER Resolution TEST CONDITIONS MIN ADS1205I TYP(1) MAX 16 UNITS Bits DC Accuracy INL Integral linearity error(2) −1.4 ±3 −0.002 ±0.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating free-air temperature range at −40°C to +85°C, AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating free-air temperature range at −40°C to +85°C, AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 PIN ASSIGNMENT 19 NC(2) 20 CH A+ 21 CH A− 22 CH B− 23 CH B+ 24 NC(2) RGE PACKAGE QFN−24 (TOP VIEW) REFIN B 1 18 REFIN A AGND 2 17 AGND AVDD 3 16 AVDD AVDD 4 15 AVDD AGND 5 14 REFOUT CLKSEL 6 13 AGND 7 8 9 10 11 12 CLKIN BVDD BGND CLKOUT OUT B OUT A ADS1205(1) (1) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 PARAMETER MEASUREMENT INFORMATION tC1 CLKIN t W1 tC2 tD1 tD2 CLKOUT tD3 tW2 tD4 OUT x Figure 1. ADS1205 Timing Diagram TIMING REQUIREMENTS(1) over recommended operating free-air temperature range at −40°C to +85°C, AVDD = 5V, and BVDD = 2.7 to 5V, unless otherwise noted. MIN 41.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 TYPICAL CHARACTERISTICS AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted. 0.00259 1.7 0.00259 1.2 0.00183 1.2 0.00183 0.70 0.00107 0.70 0.00107 0.20 0.00031 +25_C −0.00046 +85_C −0.8 −1.3 −1.8 −2.5 −2.0 −1.5 −1.0 −0.5 0 0.5 1.0 Differential Input Voltage (V) 2.0 0.00031 −0.3 −0.00122 −0.8 −0.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 TYPICAL CHARACTERISTICS (continued) AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted. OFFSET vs POWER SUPPLY REFERENCE VOLTAGE vs TEMPERATURE −0.8 2.510 2.508 2.506 2.504 CLKIN = 32MHz VREF (V) Offset (mV) −1.0 −1.2 CLKIN = 20MHz 2.502 2.500 2.498 2.496 −1.4 2.494 2.492 −1.6 4.50 2.490 4.75 5.00 5.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 TYPICAL CHARACTERISTICS (continued) AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 TYPICAL CHARACTERISTICS (continued) AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 TYPICAL CHARACTERISTICS (continued) AVDD = 5V, BVDD = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V, REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc3 filter with decimation by 256, unless otherwise noted. 10.8 10.1 10.6 10.0 10.4 9.9 10.2 10.0 9.8 9.6 9.8 9.7 9.6 9.5 9.4 9.4 9.2 9.3 9.0 −40 −20 9.2 0 20 40 Temperature (_ C) Figure 26 12 CLOCK FREQUENCY vs POWER SUPPLY 10.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 GENERAL DESCRIPTION The ADS1205 is a two-channel, 2nd-order, CMOS device with two delta-sigma modulators, designed for medium- to high-resolution A/D signal conversions from DC to 39kHz (filter response −3dB) if an oversampling ratio (OSR) of 64 is chosen. The output of the converter (OUTX) provides a stream of digital ones and zeros. The time average of this serial output is proportional to the analog input voltage.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 AVDD +5V BVD D 27Ω R1 CH A+ OP A 435 4 IN+ CH A− 0.1nF 2nd−Order ∆Σ Modulator R2 OUT A OUT B Output Interface Circuit FPGA or ASIC REFIN A CLKOUT +5V CH B+ 27Ω R1 OP A 435 4 CH B− 2nd−Order ∆Σ Modulator +3V BVD D 0.1µF BGND IN− REFIN B R2 Divider +5V +3V 27Ω R1 Clock Select OP A 435 4 IN+ CLKIN CLKSEL 0.1nF +5V R2 AVD D Out +5V 27Ω R1 OP A 435 4 IN− REFOUT R2 Reference Voltage 2.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 THEORY OF OPERATION The differential analog input of the ADS1205 is implemented with a switched-capacitor circuit. This circuit implements a 2nd-order modulator stage, which digitizes the analog input signal into a 1-bit output stream. The clock source can be internal as well as external. Different frequencies for this clock allow for a variety of solutions and signal bandwidths.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 fCLK X2 X(t) Integrator 1 X3 Integrator 2 X4 DATA fS VREF Comparator X6 D/A Converter Figure 31. Block Diagram of the 2nd-Order Modulator DIGITAL OUTPUT A differential input signal of 0V will ideally produce a stream of ones and zeros that are high 50% of the time and low 50% of the time. A differential input of +2V produces a stream of ones and zeros that are high 80% of the time.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 FILTER USAGE 0 A very simple filter, built with minimal effort and hardware, is the Sinc3 filter: ǒ Ǔ −OSR H(z) + 1 * z −1 1*z OSR = 32 f DATA = 10MHz/32 = 312.5kHz −3dB: 81.9kHz −10 −20 Gain (dB) The modulator generates only a bitstream, which does not output a digital word like an A/D converter. In order to output a digital word equivalent to the analog input voltage, the bitstream must be processed by a digital filter.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 The effective number of bits (ENOB) can be used to compare the performance of ADCs and delta-sigma modulators. Figure 35 shows the ENOB of the ADS1205 with different filter types. In this data sheet, the ENOB is calculated from the SNR: SNR = 1.76dB + 6.02dB × ENOB (3) filter types other than Sinc3 might be a better choice. A simple example is a Sinc2 filter.
www.ti.com SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 LAYOUT CONSIDERATIONS POWER SUPPLIES An applied external digital filter rejects high-frequency noise. PSRR and CMRR improve at higher frequencies because the digital filter suppresses high-frequency noise. However, the suppression of the filter is not infinite, so high-frequency noise still influences the conversion result.
Revision History DATE REV PAGE 8/06 B 6 SECTION Pin Assignment DESCRIPTION Added Note 1 to QFN package. NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com Device 10-Aug-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1205IRGER RGE 24 TAI 330 12 4.3 4.3 1.5 8 12 Q2 ADS1205IRGET RGE 24 TAI 330 12 4.3 4.3 1.5 8 12 Q2 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) ADS1205IRGER RGE 24 TAI 407.0 336.6 97.0 ADS1205IRGET RGE 24 TAI 407.0 336.6 97.
This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB.
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1205IRGER VQFN RGE 24 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS1205IRGET VQFN RGE 24 250 180.0 12.4 4.3 4.3 1.5 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1205IRGER VQFN RGE 24 3000 338.1 338.1 20.6 ADS1205IRGET VQFN RGE 24 250 210.0 185.0 35.
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