Datasheet

DIGITAL INTERFACE
INTRODUCTION
MODES OF OPERATION
0
-10
-20
-30
-40
-50
-60
-70
-80
Gain(dB)
Frequency(kHz)
0 200 400 600 800 1000 1200 1400 1600
OSR=32
f =10MHz/32=312.5kHz
3dB:81.9kHz
DATA
-
FILTER USAGE
H(z)=
1 z-
-OSR
1 z-
-1
2
(2)
30k
25k
20k
15k
10k
5k
0
OutputCode
NumberofOutputClocks
0 5 10 15 20 25 30 35 40
OSR=32
FSR=32768
ENOB=9.9Bits
SettlingTime=
3 1/f =9.6 s´ m
DATA
ADS1204
www.ti.com ........................................................................................................................................... SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009
frequency of output data rate f
DATA
= f
CLK
/OSR. The
– 3dB point is located at half the Nyquist frequency or
f
DATA
/4. For some applications, it may be necessary
The analog signal connected to the input of the Δ Σ
to use another filter type for better frequency
modulator is converted using the clock signal applied
response.
to the modulator. The result of the conversion, or
This performance can be improved, for example, by a
modulation, is generated and sent to the OUTx pin
cascaded filter structure. The first decimation stage
from the Δ Σ modulator. In most applications where a
can be a Sinc
3
filter with a low OSR and the second
direct connection is realized between the Δ Σ
stage a high-order filter.
modulator and an ASIC or FPGA (each with an
implemented filter), the two standard signals per
For more information, see application note SBAA094 ,
modulator (CLKOUT and OUTx) are provided from
Combining the ADS1202 with an FPGA Digital Filter
the modulator. The output clock signal is equal for all
for Current Measurement in Motor Control
four modulators. If CLKSEL = 1, CLKIN must always
Applications, available for download at www.ti.com .
be set either high or low.
The system clock of the ADS1204 is 20MHz by
default. The system clock can be provided either from
the internal 20MHz RC oscillator or from an external
clock source. For this purpose, the CLKIN pin is
provided; it is controlled by the mode setting,
CLKSEL.
The system clock is divided by two for the modulator
clock. Therefore, the default clock frequency of the
modulator is 10MHz. With a possible external clock
range of 1MHz to 32MHz, the modulator operates
between 500kHz and 16MHz.
Figure 31. Frequency Response of Sinc
3
Filter
The modulator generates only a bitstream, which
does not output a digital word like an A/D converter.
In order to output a digital word equivalent to the
analog input voltage, the bitstream must be
processed by a digital filter.
A very simple filter, built with minimal effort and
hardware, is the Sinc
3
filter shown in Equation 2 :
This filter provides the best output performance at the
lowest hardware size (for example, a count of digital
gates). For oversampling ratios in the range of 16 to
256, this is a good choice. All the characterizations in
the data sheet are also done using a Sinc
3
filter with
an oversampling ratio of OSR = 256 and an output
Figure 32. Pulse Response of Sinc
3
Filter
word width of 16 bits.
(f
MOD
= 10MHz)
In a Sinc
3
filter response (shown in Figure 31 and
Figure 32 ), the location of the first notch occurs at the
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