Datasheet

THEORY OF OPERATION
Z =
IN
100kW
f /10MHz
MOD
(1)
ANALOG INPUT STAGE
Analog Input
650W
650W
SwitchingFrequency=CLK
High
Impedance
>1GW
1.2pF
V
CM
A
IN+
1.2pF
0.4pF
0.4pF
A
IN-
High
Impedance
>1GW
ADS1204
www.ti.com ........................................................................................................................................... SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009
which is also the sampling frequency of the
modulator. Figure 28 shows the basic input structure
The differential analog input of the ADS1204 is
of one channel of the ADS1204. The relationship
implemented with a switched-capacitor circuit. This
between the input impedance of the ADS1204 and
circuit implements a second-order modulator stage,
the modulator clock frequency is shown in
which digitizes the analog input signal into a 1-bit
Equation 1 :
output stream. The clock source can be internal as
well as external. Different frequencies for this clock
allow for a variety of solutions and signal bandwidths.
Every analog input signal is continuously sampled by
The input impedance becomes a consideration in
the modulator and compared to a reference voltage
designs where the source impedance of the input
that is applied to the REFINx pin. A digital stream,
signal is high. This high impedance may cause
which accurately represents the analog input voltage
degradation in gain, linearity, and THD. The
over time, appears at the output of the corresponding
importance of this effect depends on the desired
converter.
system performance. There are two restrictions on
the analog input signals, CH x+ and CH x – . If the
input voltage exceeds the range (GND – 0.3V) to
(V
DD
+ 0.3V), the input current must be limited to
10mA because the input protection diodes on the
The topology of the analog inputs of ADS1204 is front end of the converter will begin to turn on. In
based on fully differential switched-capacitor addition, the linearity and the noise performance of
architecture. This input stage provides the the device are ensured only when the differential
mechanism to achieve low system noise, high analog voltage resides within ± 2V (with V
REF
as a
common-mode rejection (100dB), and excellent midpoint); however, the FSR input voltage is ± 2.5V.
power-supply rejection.
The input impedance of the analog input is
dependent on the modulator clock frequency (f
CLK
),
Figure 28. Input Impedance of the ADS1204
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