Datasheet

GENERAL DESCRIPTION
27W
5kW
5kW 2kW
2kW
+5V
0.1nF
+3V
+3V
0.1 Fm
0.1 Fm
0.1 Fm
±5V
OPA4350
0.1 Fm
27W
5kW
5kW 2kW
2kW
+5V
0.1nF
±5V
OPA4350
0.1 Fm
FPGA
or
ASIC
CH A+
AV
DD
CHA-
Output
Interface
Circuit
RC
Oscillator
20MHz
Out EN
Clock
Select
Divider
REFIN A
Reference
Voltage
2.5V
REFOUT
OUTA
OUT B
OUT C
OUT D
CLKIN
AGNDAGNDAGNDAGND
BV
DD
CLKOUT
BV
DD
BGND
+5V
0.1 Fm
+5V
0.1 Fm
+5V
0.1 Fm
+5V
0.1 Fm
CLKSEL
AV
DD
AV
DD
AV
DD
AV
DD
CHB+
CHB-
REFINB
CHC+
CHC-
REFINC
2nd-Order
DS Modulator
CHD+
CHD-
REFIND
27W
5kW
5kW 2kW
2kW
+5V
0.1nF
±5V
OPA4350
0.1 Fm
27W
5kW
5kW 2kW
2kW
+5V
+5V
0.1nF
±5V
OPA4350
OPA336
0.1 Fm
2nd-Order
DS Modulator
2nd-Order
DS Modulator
2nd-Order
DS Modulator
ADS1204
www.ti.com ........................................................................................................................................... SBAS301C – OCTOBER 2003 – REVISED FEBRUARY 2009
The ADS1204 is a four-channel, second-order, An application-specific integrated circuit (ASIC) or
CMOS device with four delta-sigma ( Δ Σ ) modulators, field-programmable gate array (FPGA) could be used
designed for medium- to high-resolution A/D signal to implement the digital filter. Figure 26 and Figure 27
conversions from dc to 39kHz (filter response – 3dB) if show typical application circuits with the ADS1204
an oversampling ratio (OSR) of 64 is chosen. The connected to an FPGA.
output of the converter (OUTX) provides a stream of
The overall performance (that is, speed and
digital ones and zeros. The time average of this serial
accuracy) depends on the selection of an appropriate
output is proportional to the analog input voltage.
OSR and filter type. A higher OSR produces greater
The modulator shifts the quantization noise to high output accuracy while operating at a lower refresh
frequencies. A low-pass digital filter should be used rate. Alternatively, a lower OSR produces lower
at the output of the Δ Σ modulator. The filter serves output accuracy, but operates at a higher refresh
two functions. First, it filters out high-frequency noise. rate. This system allows flexibility with the digital filter
Second, the filter converts the 1-bit data stream at a design and is capable of A/D conversion results that
high sampling rate into a higher-bit data word at a have a dynamic range exceeding 100dB with an OSR
lower rate (decimation). equal to 256.
Figure 26. Single-Ended Connection Diagram for the ADS1204 Δ Σ Modulator
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Product Folder Link(s): ADS1204