Datasheet

ADS1202
18
SBAS275B
www.ti.com
LAYOUT CONSIDERATIONS
POWER SUPPLIES
The ADS1202 requires only one power supply (V
DD
). If there
are separate analog and digital power supplies on the board,
a good design approach is to have the ADS1202 connected
to the analog power supply. Another possible approach to
control the noise is the use of a resistor on the power supply.
The connection can be made between the ADS1202 power-
supply pins via a 10Ω resistor. The combination of this
resistor and the decoupling capacitors between the power-
supply pins on the ADS1202 provide some filtering. The
analog supply that is used must be well regulated and
generate low noise. For designs requiring higher resolution
from the ADS1202, power-supply rejection will be a concern.
The digital power supply has high-frequency noise that can
be capacitively coupled into the analog portion of the
ADS1202. This noise can originate from switching power
supplies, microprocessors, or digital signal processors. High-
frequency noise will generally be rejected by the external
digital filter at integer multiples of MCLK. Just below and
above these frequencies, noise will alias back into the
passband of the digital filter, affecting the conversion result.
Inputs to the ADS1202, such as V
IN
+, V
IN
–, and MCLK
should not be present before the power supply is on. Violat-
ing this condition could cause latch-up. If these signals are
present before the supply is on, series resistors should be
used to limit the input current. Experimentation may be the
best way to determine the appropriate connection between
the ADS1202 and different power supplies.
GROUNDING
Analog and digital sections of the design must be carefully
and cleanly partitioned. Each section should have its own
ground plane with no overlap between them. Do not join the
ground planes, but connect the two with a moderate signal
trace underneath the converter. For multiple converters,
connect the two ground planes as close as possible to one
central location for all of the converters. In some cases,
experimentation may be required to find the best point to
connect the two planes together.
DECOUPLING
Good decoupling practices must be used for the ADS1202
and for all components in the design. All decoupling capaci-
tors, specifically the 0.1µF ceramic capacitors, must be
placed as close as possible to the pin being decoupled. A
1µF and 10µF capacitor, in parallel with the 0.1µF ceramic
capacitor, must be used to decouple V
DD
to GND. At least
one 0.1µF ceramic capacitor must be used to decouple V
DD
to GND, as well as for the digital supply on each digital
component.
FIGURE 13. Parallel Operation of ADS1202 in Mode 3.
M0
V
IN
+
V
IN
–
R
SENSE
C
1
0.1µF
C
4
0.1µF
+
–
M1
V
DD
MCLK
MDAT
GND
ADS1202
CV
DD
SPICLK
SPISIMO
SPISIMO
SPISIMO
DV
DD
CLK
C28x
or
C24x
R
1
27Ω
M0
V
IN
+
V
IN
–
R
SENSE
C
2
0.1µF
C
5
0.1µF
+
–
M1
V
DD
MCLK
MDAT
GND
ADS1202
R
2
27Ω
M0
V
IN
+
V
IN
–
R
SENSE
C
3
0.1µF
C
6
0.1µF
+
–
M1
V
DD
MCLK
MDAT
GND
ADS1202
R
3
27Ω