Datasheet

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ADS1202

SBAS275B – DECEMBER 2002 – REVISED JULY 2004

www.ti.com

DESCRIPTION

The ADS1202 is a precision, 80dB dynamic range, delta-

sigma (∆Σ) modulator operating from a single +5V supply.

The differential inputs are ideal for direct connections to

transducers or low-level signals. With the appropriate digital

filter and modulator rate, the device can be used to achieve

16-bit Analog-to-Digital (A/D) conversion with no missing

codes. Effective resolution of 12 bits can be maintained with

a digital filter bandwidth of 10kHz at a modulator rate of

10MHz. The ADS1202 is designed for use in medium reso-

lution measurement applications including current measure-

ments, smart transmitters, industrial process control, weigh

scales, chromatography, and portable instrumentation. It is

available in a TSSOP-8 package.

FEATURES

● 16-BIT RESOLUTION

● 13-BIT LINEARITY

● RESOLUTION/SPEED TRADE-OFF:

10-Bit Effective Resolution with 20µs Signal

Delay (12-bit with 77µs)

●

250mV INPUT RANGE WITH SINGLE 5V SUPPLY

● 2% INTERNAL REFERENCE VOLTAGE

● 2% GAIN ERROR

● FLEXIBLE SERIAL INTERFACE WITH FOUR

DIFFERENT MODES

● IMPLEMENTED TWINNED BINARY CODING AS

SPLIT PHASE OR MANCHESTER CODING FOR

ONE LINE INTERFACING

● OPERATING TEMPERATURE RANGE:

–40°C to +85°C

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Motor Control Current Shunt

1-Bit, 10MHz, 2nd-Order, Delta-Sigma Modulator

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

APPLICATIONS

● MOTOR CONTROL

● CURRENT MEASUREMENT

● INDUSTRIAL PROCESS CONTROL

● INSTRUMENTATION

● SMART TRANSMITTERS

● PORTABLE INSTRUMENTS

● WEIGHT SCALES

● PRESSURE TRANSDUCERS

Buffer

Reference

Voltage

2.5V

2nd-Order

∆∑ Modulator

RC Oscillator

20MHz

Interface

Circuit

MDAT

MCLK

IN+

IN–

GND

Summary of content (25 pages)

PAGE 1
ADS1202 SBAS275B – DECEMBER 2002 – REVISED JULY 2004 Motor Control Current Shunt 1-Bit, 10MHz, 2nd-Order, Delta-Sigma Modulator FEATURES DESCRIPTION ● 16-BIT RESOLUTION The ADS1202 is a precision, 80dB dynamic range, deltasigma (∆Σ) modulator operating from a single +5V supply. The differential inputs are ideal for direct connections to transducers or low-level signals.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature (unless otherwise noted)(1) Supply Voltage, GND to VDD ................................................. –0.3V to 6V Analog Input Voltage Range ......................... GND – 0.4V to VDD + 0.3V Digital Input Voltage Range .......................... GND – 0.3V to VDD + 0.3V Power Dissipation ............................................................................ 0.
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ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at –40°C to +85°C, VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted.
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TIMING DIAGRAMS tC1 MCLK tW1 tD1 MDAT DIAGRAM 1: Mode 0 Operation. tC2 MCLK tD2 tW2 tD3 MDAT DIAGRAM 2: Mode 1 Operation. tC1 MCLK tw1 tC3 MDAT tw3 1 0 1 1 0 0 DIAGRAM 3: Mode 2 Operation. 4 ADS1202 www.ti.
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TIMING DIAGRAMS (Cont.) tC4 MCLK tw4 tD4 MDAT DIAGRAM 4: Mode 3 Operation. TIMING CHARACTERISTICS over recommended operating free-air temperature range –40°C to +85°C, VDD = 5V, and MCLK = 10MHz, unless otherwise noted.
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TYPICAL CHARACTERISTICS VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted.
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TYPICAL CHARACTERISTICS (Cont.) VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted. RMS NOISE vs INPUT VOLTAGE LEVEL SIGNAL-TO-NOISE RATIO vs TEMPERATURE 80 71.0 70 70.8 70.6 60 70.4 50 SNR (dB) RMS Noise (µV) Mode 0 40 30 Mode 3 70.2 70.0 69.8 69.6 20 69.4 10 69.2 0 –320 69.
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TYPICAL CHARACTERISTICS (Cont.) VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted.
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TYPICAL CHARACTERISTICS (Cont.) VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted. POWER-SUPPLY REJECTION RATIO vs FREQUENCY HISTOGRAM OF OUTPUT DATA 2000 85 1800 Number of Occurrences 90 75 70 65 60 1600 1400 1200 1000 800 600 400 55 200 50 –626 –687 –748 –809 –870 –931 100k –1114 1k 10k Frequency of Power Supply (Hz) –992 0 100 –1053 PSRR (dB) 80 ppm of FS MCLK AND MDAT TYPICAL SINK CURRENT POWER-SUPPLY CURRENT vs TEMPERATURE 70 10 5.
PAGE 10
GENERAL DESCRIPTION THEORY OF OPERATION The ADS1202 is a single-channel, 2nd-order, CMOS analog modulator designed for medium- to high-resolution conversions from dc to 39kHz with an oversampling ratio (OSR) of 256. The output of the converter (MDAT) provides a stream of digital ones and zeros. The time average of this serial output is proportional to the analog input voltage.
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ANALOG INPUT STAGE the linearity of the device is ensured only when the analog voltage applied to either input resides within the range defined by –320mV and +320mV. Analog Input The input design topology of the ADS1202 is based on a fully differential switched-capacitor architecture. This input stage provides the mechanism to achieve low system noise, high common-mode rejection (90dB), and excellent power-supply rejection.
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DIGITAL OUTPUT The timing diagram for the ADS1202 data retrieval is shown in the Timing Diagrams. When an external clock is applied to MCLK, it is used as a system clock by the ADS1202, as well as a framing clock for data out (this procedure, however, can only be utilized in mode 3). The modulator output data, which is a serial stream, is available on the MDAT pin. Typically, MDAT is read on the falling edge of MCLK.
PAGE 13
Interface Circuit M0 Decoder M1 RC Oscillator INTCLK MUX1 EXTCLK MUX4 MUX2 MCLK MUX3 Code Generator CLK/2 MDAT OCLK CLK/4 CLK DATA ∆∑ Modulator AIN FIGURE 5. Flexible Interface Block Diagram. The code generator receives the clock signal from MUX1 and generates the delta-sigma modulator clock (CLK) divided as half clock (CLK/2) and quarter clock (CLK/4). At the same time, the continuous data stream (DATA) coming from the delta-sigma modulator is elaborated by the Code Generator.
PAGE 14
Mode 0 Mode 1 In mode 0 both input signals, M0 and M1, are LOW. The control signal coming from the decoder enables the internal RC oscillator that provides the clock signal INTCLK as an input to MUX1. The control signal coming from the decoder also positions MUX1 so that the output signal, which is an input signal for the code generator, is INTCLK.
PAGE 15
Mode 2 Mode 3 In mode 2, M0 is low and M1 is HIGH (see Table I). The control signal coming from the decoder enables the internal RC oscillator that provides the clock signal INTCLK as an input to MUX1. Another control signal coming from the decoder positions MUX1 so that the output signal that is the input signal to the code generator is INTCLK. The output signal MDAT comes from the code generator because the control signal from the decoder positions MUX3 for that operation.
PAGE 16
APPLICATIONS The DSP can be directly connected at the output of two channels of the optocoupler, C28x or C24x. In this configuration, the signals arriving at C28x or C24x are standard delta-sigma modulator signals and are connected directly to the SPICLK and SPISIMO pins. Being a delta-sigma converter, there is no need to have word sync on the serial data, so an SPI is ideal for connection. McBSP would work as well in SPI mode. Mode 0 operation in a typical application is shown in Figure 10.
PAGE 17
HV+ Floating Power Supply Gated Drive Circuit R1 D1 5.1V R2 27Ω RSENSE C1 0.1µF ADS1202 M0 C2 0.1µF Power Supply R4 VIN+ MCLK VIN– MDAT M1 Optocoupler VDD C28x or C24x GND Gated Drive Circuit HV– FIGURE 11. Application Diagram in Mode 2. HV+ Floating Power Supply C28x or C24x Gate Drive Circuit CVDD ADS1202 R2 27Ω RSENSE – VDD M0 + C2 0.1µF C1 0.1µF VIN+ MCLK SPICLK VIN– MDAT SPISIMO M1 GND DVDD FIGURE 12. Application Diagram without Galvanical Isolation in Mode 0.
PAGE 18
– C1 0.1µF MCLK MDAT GND M1 C5 0.1µF VDD M0 + – VIN+ VIN– ADS1202 R2 27Ω RSENSE VDD M0 + RSENSE C4 0.1µF ADS1202 R1 27Ω C2 0.1µF VIN+ MCLK VIN– MDAT GND M1 C28x or C24x CVDD M0 + RSENSE – C6 0.1µF ADS1202 R3 27Ω C3 0.1µF VDD SPICLK VIN+ MCLK SPISIMO VIN– MDAT SPISIMO GND SPISIMO M1 DVDD CLK FIGURE 13. Parallel Operation of ADS1202 in Mode 3. LAYOUT CONSIDERATIONS used to limit the input current.
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PACKAGE DRAWING PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1202IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 ADS1202IPWT TSSOP PW 8 250 330.0 12.4 7.0 3.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1202IPWR TSSOP PW 8 2000 340.5 338.1 20.6 ADS1202IPWT TSSOP PW 8 250 340.5 338.1 20.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.