Datasheet
ADS1194, ADS1196
ADS1198
www.ti.com
SBAS471C –APRIL 2010– REVISED NOVEMBER 2011
CONFIG1: Configuration Register 1
Address = 01h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 DAISY_EN CLK_EN 0 0 DR2 DR1 DR0
Bit 7 Must always be set to '0'
Bit 6 DAISY_EN: Daisy-chain/multiple readback mode
This bit determines which mode is enabled.
0 = Daisy-chain mode (default)
1 = Multiple readback mode
Bit 5 CLK_EN: CLK connection
(1)
This bit determines if the internal oscillator signal is connected to the CLK pin when the CLKSEL pin = 1.
0 = Oscillator clock output disabled (default)
1 = Oscillator clock output enabled
Bits[4:3] Must always be set to '0'
Bits[2:0] DR[2:0]: Output data rate.
f
MOD
= f
CLK
/16.
These bits determine the output data rate of the device.
(1) Additional power will be consumed when driving external devices.
BIT DATA RATE SAMPLE RATE
(1)
000 f
MOD
/16 8kSPS
001 f
MOD
/32 4kSPS
010 f
MOD
/64 2kSPS
011 f
MOD
/128 1kSPS
100 (default) f
MOD
/256 500SPS
101 f
MOD
/512 250SPS
110 f
MOD
/1024 125SPS
111 DO NOT USE N/A
(1) f
CLK
= 2.048MHz.
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