Datasheet

DOUT
DAISY_IN
1
0
DO TU
0
SCLK
MSB
1
MSB
0
21
3 152
153
154
MSB
1
LSB
0
LSB
1
155 241
LSB
1
Daaft romfirstd ce(evi ADS1198) Daaft romsecond vide ce(ADS1194)
XX
f
SCLK
f (N )(N
DR BITS CHANNELS
)+24
N =
DEVICES
ADS1194, ADS1196
ADS1198
SBAS471C APRIL 2010 REVISED NOVEMBER 2011
www.ti.com
Note that from Figure 2, the SCLK rising edge shifts data out of the ADS1194/6/8 on DOUT. The SCLK rising
edge is also used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster
SCLK rate speed, but it also makes the interface sensitive to board level signal delays. The more devices in the
chain, the more challenging it could become to adhere to setup and hold times. A star pattern connection of
SCLK to all devices, minimizing length of DOUT, and other PCB layout techniques help. Placing delay circuits
such as buffers between DOUT and DAISY_IN are ways to mitigate this challenge. One other option is to insert a
D flip-flop between DOUT and DAISY_IN clocked on an inverted SCLK. Note also that daisy-chain mode
requires some software overhead to recombine data bits spread across byte boundaries. Figure 37 shows a
timing diagram for the daisy-chain mode.
Figure 37. Daisy-Chain Timing
The maximum number of devices that can be daisy-chained depends on the data rate at which the device is
being operated. The maximum number of devices can be approximately calculated with Equation 6.
where:
N
BITS
= device resolution (depends on data rate), and
N
CHANNELS
= number of channels in the device (4, 6, or 8). (6)
For example, when the ADS1198 (eight-channel, 16-bit version) is operated at a 2kSPS data rate with a 4MHz
f
SCLK
, 15 devices can be daisy-chained.
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Product Folder Link(s): ADS1194 ADS1196 ADS1198