Datasheet
PgaP
R
50kW
2
R
20k
(forGain=6)
W
1
R
50kW
2
FromMuxP
PgaN
FromMuxN
ToADC
AVDD 0.2- -
GainV
MAX_DIFF
2
>CM>AVSS+0.2+
GainV
MAX_DIFF
2
ADS1194, ADS1196
ADS1198
SBAS471C –APRIL 2010– REVISED NOVEMBER 2011
www.ti.com
PGA SETTINGS AND INPUT RANGE
The PGA is a differential input/differential output amplifier, as shown in Figure 19. It has seven gain settings (1,
2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CHnSET: Individual Channel
Settings subsection of the Register Map section for details). The ADS1194/6/8 have CMOS inputs and hence
have negligible current noise. Table 4 shows the typical values of bandwidths for various gain settings. Note that
Table 4 shows the small-signal bandwidth. For large signals, the performance is limited by the slew rate of the
PGA.
Figure 19. PGA Implementation
Table 4. PGA Gain versus Bandwidth
NOMINAL BANDWIDTH AT ROOM
GAIN TEMPERATURE (kHz)
1 158
2 97
3 85
4 64
6 43
8 32
12 21
The resistor string of the PGA that implements the gain has 120kΩ of resistance for a gain of 6. This resistance
provides a current path across the outputs of the PGA in the presence of a differential input signal. This current
is in addition to the quiescent current specified for the device in the presence of differential signal at input.
Input Common-Mode Range
The usable input common-mode range of the front end depends on various parameters, including the maximum
differential input signal, supply voltage, PGA gain, etc. This range is described in Equation 2:
where:
V
MAX_DIFF
= maximum differential signal at the input of the PGA
CM = common-mode range (2)
For example:
If V
DD
= 3V, gain = 6, and V
MAX_DIFF
= 350mV
Then 1.25V < CM < 1.75V
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Product Folder Link(s): ADS1194 ADS1196 ADS1198