Datasheet
ADS1194, ADS1196
ADS1198
www.ti.com
SBAS471C –APRIL 2010– REVISED NOVEMBER 2011
OVERVIEW
The ADS1194/6/8 are low-power, multichannel, simultaneously-sampling, 16-bit delta-sigma (ΔΣ)
analog-to-digital converters (ADCs) with integrated programmable gain amplifiers (PGAs). These devices
integrate various ECG-specific functions that make them well-suited for scalable electrocardiogram (ECG),
electroencephalography (EEG), and electromyography (EMG) applications. The devices can also be used in
high-performance, multichannel data acquisition systems by powering down the ECG-specific circuitry.
The ADS1194/6/8 have a highly programmable multiplexer that allows for temperature, supply, input short, and
RLD measurements. Additionally, the multiplexer allows any of the input electrodes to be programmed as the
patient reference drive. The PGA gain can be chosen from one of seven settings (1, 2, 3, 4, 6, 8, and 12). The
ADCs in the device offer data rates from 125SPS to 8kSPS. Communication to the device is accomplished using
an SPI-compatible interface. The device provides four GPIO pins for general use. Multiple devices can be
synchronized using the START pin.
The internal reference can be programmed to either 2.4V or 4V. The internal oscillator generates a 2.048MHz
clock. The versatile right leg drive (RLD) block allows the user to choose the average of any combination of
electrodes to generate the patient drive signal. Lead-off detection can be accomplished either by using a
pull-up/pull-down resistor or a current source/sink. An internal ac lead-off detection feature is also available. The
device supports both hardware pace detection and software pace detection. The Wilson center terminal (WCT)
block can be used to generate the WCT point of the standard 12-lead ECG.
THEORY OF OPERATION
This section contains details of the ADS1194/6/8 internal functional elements; see Figure 14. The analog blocks
are discussed first, followed by the digital interface. Blocks implementing ECG-specific functions are covered at
the end.
Throughout this document, f
CLK
denotes the frequency of the signal at the CLK pin, t
CLK
denotes the period of the
signal at the CLK pin, f
DR
denotes the output data rate, t
DR
denotes the time period of the output data, and f
MOD
denotes the frequency at which the modulator samples the input.
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