Datasheet

ADS1194, ADS1196
ADS1198
SBAS471C –APRIL 2010– REVISED NOVEMBER 2011 www.ti.com
LOFF: Lead-Off Control Register
Address = 04h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
COMP_TH2 COMP_TH1 COMP_TH0 VLEAD_OFF_EN ILEAD_OFF1 ILEAD_OFF0 FLEAD_OFF1 FLEAD_OFF0
The Lead-Off Control Register configures the Lead-Off detection operation.
Bits[7:5] COMP_TH[2:0]: Lead-off comparator threshold
These bits determine the lead-off comparator threshold level setting. See the Lead-Off Detection subsection of the
ECG-Specific Functions section for a detailed description.
Comparator positive side
000 = 95% (default)
001 = 92.5%
010 = 90%
011 = 87.5%
100 = 85%
101 = 80%
110 = 75%
111 = 70%
Comparator negative side
000 = 5% (default)
001 = 7.5%
010 = 10%
011 = 12.5%
100 = 15%
101 = 20%
110 = 25%
111 = 30%
Bit 4 VLEAD_OFF_EN: Lead-off detection mode
This bit determines the lead-off detection mode.
0 = Current source mode lead-off (default)
1 = Pull-up/pull-down resistor mode lead-off
Bits[3:2] ILEAD_OFF[1:0]: Lead-off current magnitude
These bits determine the magnitude of current for the current lead-off mode.
00 = 4nA (default)
01 = 8nA
10 = 12nA
11 = 16nA
Bits[1:0] FLEAD_OFF[1:0]: Lead-off frequency
These bits determine the frequency of lead-off detect for each channel.
00 = When any bits of the LOFF_SENSP and LOFF_SENSN registers are turned on, make sure FLEAD_OFF[1:0] is either
set to '01' or '11' (default)
01 = AC lead-off detection at f
DR
/4
10 = Do not use
11 = DC lead-off detection turned on
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