Datasheet

ADS1194, ADS1196

ADS1198

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SBAS471C –APRIL 2010– REVISED NOVEMBER 2011

CONFIG3: Configuration Register 3

Address = 03h

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

PD_REFBUF 1 VREF_4V RLD_MEAS RLDREF_INT PD_RLD RLD_LOFF_SENS RLD_STAT

Configuration Register 3 configures multi-reference and RLD operation.

Bit 7 PD_REFBUF: Power-down reference buffer

This bit determines the power-down reference buffer state.

0 = Power-down internal reference buffer (default)

1 = Enable internal reference buffer

Bit 6 Must always be set to '1'. Default is '1' at power-up.

Bit 5 VREF_4V: Reference voltage

This bit determines the reference voltage, VREFP.

0 = VREFP is set to 2.4V (default)

1 = VREFP is set to 4V (use only with a 5V analog supply)

Bit 4 RLD_MEAS: RLD measurement

This bit enables RLD measurement. The RLD signal may be measured with any channel.

0 = Open (default)

1 = RLD_IN signal is routed to the channel that has the MUX_Setting 010 (V

REF

)

Bit 3 RLDREF_INT: RLDREF signal

This bit determines the RLDREF signal source.

0 = RLDREF signal fed externally (default)

1 = RLDREF signal (AVDD – AVSS)/2 generated internally

Bit 2 PD_RLD: RLD buffer power

This bit determines the RLD buffer power state.

0 = RLD buffer is powered down (default)

1 = RLD buffer is enabled

Bit 1 RLD_LOFF_SENS: RLD sense selection

This bit enables the RLD sense function.

0 = RLD sense is disabled (default)

1 = RLD sense is enabled

Bit 0 RLD_STAT: RLD lead off status

This bit determines the RLD status.

0 = RLD is connected (default)

1 = RLD is not connected

Product Folder Link(s): ADS1194 ADS1196 ADS1198