Datasheet

ADS1194, ADS1196
ADS1198
www.ti.com SBAS471C –APRIL 2010– REVISED NOVEMBER 2011
REGISTER MAP
Table 10 describes the various ADS1194/6/8 registers.
Table 10. Register Assignments
RESET
VALUE
ADDRESS REGISTER (Hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Device Settings (Read-Only Registers)
00h ID XX DEV_ID5 DEV_ID4 DEV_ID3 1 0 DEV_ID2 DEV_ID1 DEV_ID0
Global Settings Across Channels
01h CONFIG1 04 0 DAISY_EN CLK_EN 0 0 DR2 DR1 DR0
02h CONFIG2 20 0 0 1 INT_TEST 0 TEST_AMP TEST_FREQ1 TEST_FREQ0
RLD_LOFF_
03h CONFIG3 40 PD_REFBUF 1 VREF_4V RLD_MEAS RLDREF_INT PD_RLD RLD_STAT
SENS
VLEAD_OFF_
04h LOFF 00 COMP_TH2 COMP_TH1 COMP_TH0 ILEAD_OFF1 ILEAD_OFF0 FLEAD_OFF1 FLEAD_OFF0
EN
Channel-Specific Settings
05h CH1SET 00 PD1 GAIN12 GAIN11 GAIN10 0 MUXn2 MUXn1 MUXn0
06h CH2SET 00 PD2 GAIN22 GAIN21 GAIN20 0 MUX22 MUX21 MUX20
07h CH3SET 00 PD3 GAIN32 GAIN31 GAIN30 0 MUX32 MUX31 MUX30
08h CH4SET 00 PD4 GAIN42 GAIN41 GAIN40 0 MUX42 MUX41 MUX40
09h CH5SET
(1)
00 PD5 GAIN52 GAIN51 GAIN50 0 MUX52 MUX51 MUX50
0Ah CH6SET
(1)
00 PD6 GAIN62 GAIN61 GAIN60 0 MUX62 MUX61 MUX60
0Bh CH7SET
(1)
00 PD7 GAIN72 GAIN71 GAIN70 0 MUX72 MUX71 MUX70
0Ch CH8SET
(1)
00 PD8 GAIN82 GAIN81 GAIN80 0 MUX82 MUX81 MUX80
0Dh RLD_SENSP
(2)
00 RLD8P
(1)
RLD7P
(1)
RLD6P
(1)
RLD5P
(1)
RLD4P RLD3P RLD2P RLD1P
0Eh RLD_SENSN
(2)
00 RLD8N
(1)
RLD7N
(1)
RLD6N
(1)
RLD5N
(1)
RLD4N RLD3N RLD2N RLD1N
0Fh LOFF_SENSP
(2)
00 LOFF8P LOFF7P LOFF6P LOFF5P LOFF4P LOFF3P LOFF2P LOFF1P
10h LOFF_SENSN
(2)
00 LOFF8N LOFF7N LOFF6N LOFF5N LOFF4N LOFF3N LOFF2N LOFF1N
11h LOFF_FLIP 00 LOFF_FLIP8 LOFF_FLIP7 LOFF_FLIP6 LOFF_FLIP5 LOFF_FLIP4 LOFF_FLIP3 LOFF_FLIP2 LOFF_FLIP1
Lead-Off Status Registers (Read-Only Registers)
12h LOFF_STATP 00 IN8P_OFF IN7P_OFF IN6P_OFF IN5P_OFF IN4P_OFF IN3P_OFF IN2P_OFF IN1P_OFF
13h LOFF_STATN 00 IN8N_OFF IN7N_OFF IN6N_OFF IN5N_OFF IN4N_OFF IN3N_OFF IN2N_OFF IN1N_OFF
GPIO and OTHER Registers
14h GPIO 0F GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1
15h PACE 00 0 0 0 PACEE1 PACEE0 PACEO1 PACEO0 PD_PACE
16h RESERVED 00 0 0 0 0 0 0 0 0
SINGLE_ WCT_TO_ PD_LOFF_
17h CONFIG4 00 0 0 0 0 0
SHOT RLD COMP
18h WCT1 00 aVF_CH6 aVL_CH5 aVR_CH7 avR_CH4 PD_WCTA WCTA2 WCTA1 WCTA0
19h WCT2 00 PD_WCTC PD_WCTB WCTB2 WCTB1 WCTB0 WCTC2 WCTC1 WCTC0
(1) CH5SET and CH6SET are not available for the ADS1194. CH7SET and CH8SET registers are not available for the ADS1194 and
ADS1196.
(2) The RLD_SENSP, PACE_SENSP, LOFF_SENSP, LOFF_SENSN, and LOFF_FLIP registers bits[5:4] are not available for the
ADS1194. Bits[7:6] are not available for the ADS1194/6.
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