Datasheet

Hi-Z
START
DRDY
CS
SCLK
DIN
DOUT
RDATAOpcode
Status Register+8-ChannelData(152 Bits)
RDATAOpcode
ADS1194, ADS1196
ADS1198
www.ti.com SBAS471C –APRIL 2010– REVISED NOVEMBER 2011
RDATA: Read Data
Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode).
There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent
commands or data retrieval SCLKs. To retrieve data from the device after RDATA command is issued, make
sure either the START pin is high or the START command is issued. When reading data with the RDATA
command, the read operation can overlap the occurrence of the next DRDY without data corruption. Figure 39
shows the recommended ways to use the RDATA command. RDATA is best suited for ECG and EEG type
systems, where register setting must be read or changed often between conversion cycles.
Figure 39. RDATA Usage
Sending Multi-Byte Commands
The ADS1194/6/8 serial interface decodes commands in bytes and requires four CLK cycles to decode and
execute. Therefore, when sending multi-byte commands, a period of four CLKs must separate the end of one
byte (or opcode) and the next.
Assume CLK is 2.048MHz, then t
SDECODE
(4 t
CLK
) is 1.96µs. When SCLK is 16MHz, one byte can be transferred
in 500ns. This byte transfer time does not meet the t
SDECODE
specification; therefore, a delay must be inserted so
the end of the second byte arrives 1.46µs later. If SCLK is 4MHz, one byte is transferred in 2µs. Because this
transfer time exceeds the t
SDECODE
specification, the processor can send subsequent bytes without delay. In this
later scenario, the serial port can be programmed to cease single-byte transfer per cycle to multiple bytes.
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Product Folder Link(s): ADS1194 ADS1196 ADS1198