Datasheet
START
DRDY
CS
SCLK
DIN
t
UPDATE
DOUT
Hi-Z
RDATACOpcode
StatusRegister+8-ChannelData(152Bits)
NextData
ADS1194, ADS1196
ADS1198
SBAS471C –APRIL 2010– REVISED NOVEMBER 2011
www.ti.com
STOP: Stop Conversions
This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP
command is sent, the conversion in progress completes and further conversions are stopped. If conversions are
already stopped, this command has no effect. There are no restrictions on the SCLK rate for this command and it
can be issued any time.
RDATAC: Read Data Continuous
This opcode enables the output of conversion data on each DRDY without the need to issue subsequent read
data opcodes. This mode places the conversion data in the output register and may be shifted out directly. The
read data continuous mode is the default mode of the device and the device defaults in this mode on power-up.
RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, a
SDATAC command must be issued before any other commands can be sent to the device. There is no
restriction on the SCLK rate for this command. However, the subsequent data retrieval SCLKs or the SDATAC
opcode command should wait at least 4 CLK cycles. The timing for RDATAC is shown in Figure 38. As Figure 38
shows, there is a keep out zone of 4 CLK cycles around the DRDY pulse where this command cannot be issued
in. If no data are retrieved from the device, DOUT and DRDY behave similarly in this mode. To retrieve data from
the device after RDATAC command is issued, make sure either the START pin is high or the START command
is issued. Figure 38 shows the recommended way to use the RDATAC command. RDATAC is ideally suited for
applications such as data loggers or recorders where registers are set once and do not need to be re-configured.
(1) t
UPDATE
= 4/f
CLK
. Do not read data during this time.
Figure 38. RDATAC Usage
SDATAC: Stop Read Data Continuous
This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this
command, but the following command must wait for 4 CLK cycles.
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