Datasheet

START
DRDY
4f/
CLK
4f/
CLK
DataUpdating
t
SETTLE
ADS1194, ADS1196
ADS1198
www.ti.com SBAS471C –APRIL 2010– REVISED NOVEMBER 2011
Single-Shot Mode
The single-shot mode is enabled by setting the SINGLE_SHOT bit in CONFIG4 register to '1'. In single-shot
mode, the ADS1194/6/8 perform a single conversion when the START pin is taken high for at least two t
CLK
s, or
when the START opcode command is sent. As seen in Figure 34, when a conversion is complete, DRDY goes
low and further conversions are stopped. Regardless of whether the conversion data are read or not, DRDY
remains low. To begin a new conversion, take the START pin low and then back high, or transmit the START
opcode again. Note that when switching from continuous mode to pulse mode, make sure the START signal is
pulsed or issue a STOP command followed by a START command.
Figure 34. DRDY with No Data Retrieval in Single-Shot Mode
This conversion mode is provided for applications that require a non-standard or non-continuous data rate.
Issuing a START command or toggling the START pin high resets the digital filter, effectively dropping the data
rate by a factor of four. This mode leaves the system more susceptible to aliasing effects, requiring more
complex analog or digital filtering. Loading on the host processor increases because it must toggle the START
pin or send a START command to initiate a new conversion cycle.
MULTIPLE DEVICE CONFIGURATION
The ADS1194/6/8 are designed to provide configuration flexibility when multiple devices are used in a system.
The SPI interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one additional chip select signal
per device, multiple devices can be connected together. The number of signals needed to interface n devices is
3 + n.
The right-leg drive amplifiers can be daisy-chained as explained in the RLD Configuration with Multiple Devices
subsection of the ECG-Specific Functions section. To use the internal oscillator in a daisy-chain configuration,
one of the devices must be set as the master for the clock source with the internal oscillator enabled (CLKSEL
pin = 1) and the internal oscillator clock brought out of the device by setting the CLK_EN register bit. This master
device clock is used as the external clock source for the other devices.
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Product Folder Link(s): ADS1194 ADS1196 ADS1198