Datasheet

DRDY

DOUT

SCLK

Bit151

Bit150

Bit149

GPIOPin

GPIOData(read)

GPIOData(write)

GPIOControl

ADS1194, ADS1196

ADS1198

SBAS471C –APRIL 2010– REVISED NOVEMBER 2011

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Data Ready (DRDY)

DRDY is an output. When it transitions low, new conversion data are ready. The CS signal has no effect on the

data ready signal. The behavior of DRDY is determined by whetehr the device is in RDATAC mode or the

RDATA command is being used to read data on demand. (See the RDATAC: Read Data Continuous and

RDATA: Read Data subsections of the SPI Command Definitions section for further detials). Regardless of the

status of the CS signal, a rising edge on SCLK pulls DRDY high. Hence, when using multiple devices in the SPI

bus, it is recommended that SCLK be gated with CS. When reading data with the RDATA command, the read

operation can overlap the occurrence of the next DRDY without data corruption. The START pin or the START

command is used to place the device either in normal data capture mode or pulse data capture mode. Figure 29

shows the relationship between DRDY, DOUT, and SCLK during data retrieval (in case of an ADS1198). DOUT

is latched at the rising edge of SCLK. DRDY is pulled high at the falling edge of SCLK. Note that DRDY goes

high on the first falling edge SCLK regardless of whether data are being retrieved from the device or a command

is being sent through the DIN pin.

Figure 29. DRDY with Data Retrieval (CS = 0 in RDATA Mode)

GPIO

The ADS1194/6/8 have a total of four general-purpose digital I/O (GPIO) pins available in the normal mode of

operation. The digital I/O pins are individually configurable as either inputs or as outputs through the GPIOC bits

data returned are the level of the pins, whether they are programmed as inputs or outputs. When the GPIO pin is

configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an output, a

write to the GPIOD bit sets the output value.

If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on

or after a reset. Figure 30 shows the GPIO port structure.

GPIO1 can be used as the PACEIN signal; GPIO2 is multiplexed with RESP_BLK signal; GPIO3 is multiplexed

with the RESP signal; and GPIO4 is multiplexed with the RESP_PH signal.

Figure 30. GPIO Port Pin

Power-Down (PWDN)

When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin

high. Upon exiting from power-down mode, the internal oscillator and the reference require a wake-up time. It is

recommended that during power-down the external clock is shut down to save power.

Product Folder Link(s): ADS1194 ADS1196 ADS1198