Datasheet

CS
SCLK
DRDY
DOUT
STAT
24-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
152SCLKs
DIN
ADS1194, ADS1196
ADS1198
www.ti.com SBAS471C –APRIL 2010– REVISED NOVEMBER 2011
Data Output (DOUT)
The data output pin (DOUT) is used with SCLK to read conversion and register data from the ADS1194/6/8. Data
on DOUT are shifted out on the rising edge of SCLK. DOUT goes to a high-impedance state when CS is high. In
read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line
also indicates when new data are available. This feature can be used to minimize the number of connections
between the device and the system controller. The START signal must be high or the START command must be
issued before retrieving data from the device.
Figure 28 shows the data output protocol for ADS1198.
Figure 28. SPI Bus Data Output for the ADS1198 (8-Channels)
Data Retrieval
Data retrieval can be accomplished in one of two methods. The read data continuous command can be used to
set the device in a mode to read the data continuously without sending opcodes. The read data command can be
used to read just one data output from the device (see the SPI Command Definitions section for more details).
The conversion data are read by shifting the data out on DOUT. The MSB of the data on DOUT is clocked out on
the first SCLK rising edge. DRDY returns to high on the first SCLK falling edge. DIN should remain low for the
entire read operation.
The number of bits in the data output depends on the number of channels and the number of bits per channel.
For the ADS1198, the number of data outputs is (24 status bits + 16 bits × 8 channels = 152 bits) for all data
rates. The format of the 24 status bits is: (1100 + LOFF_STATP + LOFF_STATN + bits[4:7] of the GPIO
register). The data format for each channel data are twos complement and MSB first. When channels are
powered down using the user register setting, the corresponding channel output is set to '0'. However, the
sequence of channel outputs remains the same. For the ADS1194 and the ADS1196, the last four and two
channel outputs shown in Figure 28 are zeros. Status and GPIO register bits are loaded into the 24-bit status
word 2t
CLK
s before DRDY goes low.
The ADS1194/6/8 also provide a multiple readback feature. The data can be read out multiple times by simply
giving more SCLKs, in which case the MSB data byte repeats after reading the last byte. The DAISY_EN bit in
CONFIG1 register must be set to '1' for multiple readbacks.
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Product Folder Link(s): ADS1194 ADS1196 ADS1198