Datasheet

1
CS
SCLK
DIN
DOUT
2
3 8
1 2
83
t
CSSC
t
DIST
t
DIHD
t
DOHD
t
CSH
t
DOPD
t
SPWH
t
SPWL
t
SCCS
Hi-Z
t
CSDOZ
t
CSDOD
Hi-Z
t
SCLK
t
SDECODE
CLK
t
CLK
D ISY_INA
DOUT
SCLK
MSB
D1
t
DISCK2ST
MSB
21
3 152
153
154
MSB
D1
LSB
t
DISCK2HT
t
DOPD
Don’tCare
LSB
D1
155
ADS1194, ADS1196
ADS1198
SBAS471C –APRIL 2010– REVISED NOVEMBER 2011 www.ti.com
TIMING CHARACTERISTICS
NOTE: SPI settings are CPOL = 0 and CPHA = 1.
Figure 1. Serial Interface Timing
NOTE: Daisy-chain timing is shown for the 8-channel ADS1198.
Figure 2. Daisy-Chain Interface Timing
Timing Requirements For Figure 1 and Figure 2
Specifications apply from 0°C to +70°C. Load on D
OUT
= 20pF || 100kΩ.
2.7V ≤ DVDD ≤ 3.6V 1.65V ≤ DVDD ≤ 2.0V
PARAMETER DESCRIPTION MIN TYP MAX MIN TYP MAX UNIT
t
CLK
Master clock period 414 514 414 514 ns
t
CSSC
CS low to first SCLK; setup time 6 17 ns
t
SCLK
SCLK period 50 66.6 ns
t
SPWH, L
SCLK pulse width, high and low 15 25 ns
t
DIST
DIN valid to SCLK falling edge; setup time 10 10 ns
t
DIHD
Valid DIN after SCLK falling edge; hold time 10 11 ns
t
DOHD
SCLK falling edge to invalid DOUT; hold time 10 10 ns
t
DOPD
SCLK rising edge to DOUT valid; setup time 17 32 ns
t
CSH
CS high pulse 2 2 t
CLKs
t
CSDOD
CS low to DOUT driven 8 20 ns
t
SCCS
Eighth SCLK falling edge to CS high 4 4 t
CLKs
t
SDECODE
Command decode time 4 4 t
CLKs
t
CSDOZ
CS high to DOUT Hi-Z 10 20 ns
t
DISCK2ST
DAISY_IN valid to SCLK rising edge; setup time 10 10 ns
t
DISCK2HT
DAISY_IN valid after SCLK rising edge; hold time 10 10 ns
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Product Folder Link(s): ADS1194 ADS1196 ADS1198