Datasheet

CLK
t
CPW
t
CLK
t
CPW
t
SD
t
SCLK
t
DIST
t
DOHD
t
SPW
Bit15(MSB) Bit14 Bit13
t
SPW
t
DOPD
t
CD
t
DS
t
MSBPD
t
DIHD
· · ·
t
CONV
DRDY
SCLK
DOUT
DIN
TIMING REQUIREMENTS: SPI FORMAT
ADS1174
ADS1178
www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008
TIMING CHARACTERISTICS: SPI FORMAT
For T
A
= – 40 ° C to +105 ° C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.
SYMBOL PARAMETER MIN TYP MAX UNIT
t
CLK
CLK period (1/f
CLK
)
(1)
37 10,000 ns
t
CPW
CLK positive or negative pulse width 15 ns
t
CONV
Conversion period (1/f
DATA
)
(2)
256 2560 t
CLK
t
CD
(3)
Falling edge of CLK to falling edge of DRDY 22 ns
t
DS
(3)
Falling edge of DRDY to rising edge of first SCLK to retrieve data 1 t
CLK
t
MSBPD
DRDY falling edge to DOUT MSB valid (propagation delay) 16 ns
t
SD
(3)
Falling edge of SCLK to rising edge of DRDY 18 ns
t
SCLK
(4)
SCLK period 1 t
CLK
t
SPW
SCLK positive or negative pulse width 0.4 t
CLK
t
DOHD
(3) (5)
SCLK falling edge to new DOUT invalid (hold time) 10 ns
t
DOPD
(3)
SCLK falling edge to new DOUT valid (propagation delay) 32 ns
t
DIST
New DIN valid to falling edge of SCLK (setup time) 6 ns
t
DIHD
(5)
Old DIN valid to falling edge of SCLK (hold time) 6 ns
(1) f
CLK
= 27MHz maximum.
(2) Depends on MODE[1:0] and CLKDIV selection. See Table 4 (f
CLK
/f
DATA
).
(3) Load on DRDY and DOUT = 20pF.
(4) For best performance, limit f
SCLK
/f
CLK
to ratios of 1, 1/2, 1/4, 1/8, etc.
(5) t
DOHD
(DOUT hold time) and t
DIHD
(DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and
ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is > 4ns.
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