Datasheet

FORMAT[2:0] SERIAL INTERFACE PROTOCOLS
SPI SERIAL INTERFACE
SCLK
DATA FORMAT
DRDY/FSYNC (SPI Format)
) V
REF
2
15
* 1
* V
REF
2
15
* 1
v −V
REF
ǒ
2
15
2
15
* 1
Ǔ
DRDY
SCLK
1/f
DATA
1/f
CLK
ADS1174
ADS1178
www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008
Data can be read from the ADS1174/78 with two Data are retrieved from the ADS1174/78 using the
serial interface protocols (SPI or Frame-Sync) and serial interface. Two protocols are available: SPI and
several options of data formats (TDM/Discrete and Frame-Sync. The same pins are used for both
Fixed/Dynamic data positions). The FORMAT[2:0] interfaces: SCLK, DRDY/FSYNC, DOUT[4:1] (or
inputs are used to select among the options. Table 10 DOUT[8:1] for the ADS1178), and DIN. The
lists the available options. See the DOUT Modes FORMAT[2:0] pins select the desired interface
section for details of the DOUT modes and data protocol.
positions.
Table 10. Data Output Format
The SPI-compatible format is a simple read-only
INTERFACE DOUT DATA
interface. Data ready for retrieval are indicated by the
FORMAT[2:0] PROTOCOL MODE POSITION
falling DRDY output and are shifted out on the falling
000 SPI TDM Dynamic
edge of SCLK, MSB first. The interface can be
001 SPI TDM Fixed daisy-chained using the DIN input when using
multiple ADS1174/78s. See the Daisy-Chaining
010 SPI Discrete —
section for more information.
011 Frame-Sync TDM Dynamic
100 Frame-Sync TDM Fixed
101 Frame-Sync Discrete —
The serial clock (SCLK) features a Schmitt-triggered
input and shifts out data on DOUT on the falling
edge. It also shifts in data on the falling edge on DIN
when this pin is being used for daisy-chaining. The
The ADS1174/78 outputs 16 bits of data in two ’ s
device shifts data out on the falling edge and the user
complement format.
typically shifts this data in on the rising edge. Even
A positive full-scale input produces an ideal output
though the SCLK input has hysteresis, it is
code of 7FFFh, and the negative full-scale input
recommended to keep SCLK as clean as possible to
produces an ideal output code of 8000h. The output
prevent glitches from accidentally shifting the data.
clips at these codes for signals exceeding full-scale.
SCLK may be run as fast as the CLK frequency.
Table 11 summarizes the ideal output codes for
SCLK may be either in free-running or stop-clock
different input signals.
operation between conversions. For best
performance, use f
SCLK
/f
CLK
ratios of 1, 1/2, 1/4, 1/8,
Table 11. Ideal Output Code versus Input Signal
etc. NOTE: One CLK period is required after DRDY
falls, to start shifting data (see Timing Requirements:
INPUT SIGNAL V
IN
(AINP – AINN) IDEAL OUTPUT CODE
(1)
SPI Format ).
≥ +V
REF
7FFFh
0001h
In the SPI format, this pin functions as the DRDY
output. It goes low when data are ready for retrieval
0 0000h
and then returns high on the falling edge of the first
subsequent SCLK. If data are not retrieved (that is,
FFFFh
SCLK is held low), DRDY pulses high just before the
next conversion data are ready, as shown in
Figure 16 . The new data are loaded within one CLK
8000h
cycle before DRDY goes low. All data must be shifted
out before this time to avoid being overwritten.
(1) Excludes effects of noise, INL, offset, and gain errors.
Figure 16. DRDY Timing with No Readback
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