Datasheet

MODE SELECTION (MODE) SYNCHRONIZATION ( SYNC)
MODE
ADS1174/78
Mode
NewMode
NewMode
ValidDataReady
DRDY
SPI
Protocol
Frame-Sync
Protocol
t
NDR-SPI
DOUT
NewMode
ValidDataonDOUT
t
NDR-FS
Previous
Mode
ADS1174
ADS1178
SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com
The ADS1174/78 supports two modes of operation: The ADS1174/78 can be synchronized by pulsing the
High-Speed and Low-Power. These modes offer SYNC pin low and then returning the pin high. When
optimization of speed and power. The mode selection the pin goes low, the conversion process stops, and
is determined by the status of the digital input MODE the internal counters used by the digital filter are
pins, as shown in Table 5 . The ADS1174/78 reset. When the SYNC pin returns high, the
constantly monitors the status of the MODE pin conversion process restarts. Synchronization allows
during operation. the conversion to be aligned with an external event,
such as a reference timing pulse.
Table 5. Mode Selection
Since the converters of the ADS1174/78 operate in
MODE MODE SELECTION MAX f
DATA
(1)
parallel from the same master clock and use the
0 High-Speed 52,734
same SYNC input control, they are, by default, in
1 Low-Power 10,547 synchronization with each other. However, the
synchronization of multiple ADS1174/78s is
(1) f
CLK
= 27MHz (CLKDIV = 1).
somewhat different. At device power-on, variations in
When using the SPI protocol, DRDY is held high after
internal reset thresholds from device to device may
a mode change occurs until settled (or valid) data are
result in uncertainty in conversion timing.
ready, as shown in Figure 12 and Table 6 .
The SYNC pin can be used to synchronize multiple
In Frame-Sync protocol, the DOUT pins are held low
ADS1174/78s to within the same CLK cycle.
after a mode change occurs until settled data are
Figure 13 illustrates the timing requirement of SYNC
ready, as shown in Figure 12 and Table 6 . Data can
and CLK in SPI format.
be read from the device to detect when DOUT
See Figure 14 for the Frame-Sync format timing
changes to logic 1, indicating valid data.
requirement.
Figure 12. Mode Change Timing
Table 6. Mode Change
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
NDR-SPI
Time for new data to be ready (SPI) 129 Conversions (1/f
DATA
)
t
NDR-FS
Time for new data to be ready (Frame-Sync) 127 128 Conversions (1/f
DATA
)
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