Datasheet

SCLK
FSYNC
DOUT
DIN
t
DOHD
t
FPW
t
SCLK
t
SF
t
SPW
t
SPW
t
FRAME
t
FPW
t
FS
t
DIHD
t
MSBPD
t
DIST
Bit15(MSB) Bit14 Bit13
t
DOPD
CLK
t
CPW
t
CPW
t
CS
t
CLK
TIMING REQUIREMENTS: FRAME-SYNC FORMAT
ADS1174
ADS1178
SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com
TIMING CHARACTERISTICS: FRAME-SYNC FORMAT
For T
A
= – 40 ° C to +105 ° C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.
SYMBOL PARAMETER MIN TYP MAX UNIT
t
CLK
CLK period (1/f
CLK
) 37 10,000 ns
t
CPW
CLK positive or negative pulse width 12 ns
t
CS
Falling edge of CLK to falling edge of SCLK – 0.25 0.25 t
CLK
t
FRAME
Frame period (1/f
DATA
)
(1)
256 2560 t
CLK
t
FPW
FSYNC positive or negative pulse width 1 t
SCLK
t
FS
Rising edge of FSYNC to rising edge of SCLK 5 ns
t
SF
Rising edge of SCLK to rising edge of FSYNC 5 ns
t
SCLK
SCLK period
(2)
1 t
CLK
t
SPW
SCLK positive or negative pulse width 0.4 t
CLK
t
DOHD
(3) (4)
SCLK falling edge to old DOUT invalid (hold time) 10 ns
t
DOPD
(4)
SCLK falling edge to new DOUT valid (propagation delay) 31 ns
t
MSBPD
FSYNC rising edge to DOUT MSB valid (propagation delay) 31 ns
t
DIST
New DIN valid to falling edge of SCLK (setup time) 6 ns
t
DIHD
(3)
Old DIN valid to falling edge of SCLK (hold time) 6 ns
(1) Depends on MODE[1:0] and CLKDIV selection. See Table 4 (f
CLK
/f
DATA
).
(2) SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of f
CLK
.
(3) t
DOHD
(DOUT hold time) and t
DIHD
(DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and
ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is > 4ns.
(4) Load on DOUT = 20pF.
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