Datasheet

PowerPAD PCB Layout Considerations for the
Additional PowerPAD Package Information
13mils(0.33mm)
Package
ThermalPad
Component
Traces
ThermalVia
Component(top)Side
GroundPlane
PowerPlane
Solder(bottom)Side
ThermalIsolation
(powerplaneonly)
Package
ThermalPad
(bottomtrace)
ADS1174
ADS1178
www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008
The via connections to the thermal pad and internal
ADS1174/78
ground plane should be plated completely around the
hole, as opposed to the typical web or spoke thermal
Figure 30 shows the recommended layer structure for
relief connection. Plating entirely around the thermal
thermal management when using a PowerPad
via provides the most efficient thermal connection to
package on a 4-layer PCB design. Note that the
the ground plane.
thermal pad is placed on both the top and bottom
sides of the board. The ground plane is used as the
heat-sink, while the power plane is thermally isolated
from the thermal vias.
Texas Instruments publishes the PowerPAD
Thermally-Enhanced Package Application Report (TI
Figure 31 shows the required thermal pad etch
literature number SLMA002 ), available for download
pattern for the 64-lead HTQFP package used for the
at www.ti.com , which provides a more detailed
ADS1174/78. Nine 13mil (0.33mm) thermal vias
discussion of PowerPAD design and layout
plated with one ounce of copper are placed within the
considerations. Before attempting a board layout with
thermal pad area for the purpose of connecting the
the ADS1174/78, it is recommended that the
pad to the ground plane layer. The ground plane is
hardware engineer and/or layout designer be familiar
used as a heatsink in this application. It is very
with the information contained in this document .
important that the thermal via diameter be no larger
than 13mils in order to avoid solder wicking during
the reflow process. Solder wicking results in thermal
voids that reduce heat dissipation efficiency and
hamper heat flow away from the IC die.
Figure 30. Recommended PCB Structure for a 4-Layer Board
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Product Folder Link(s): ADS1174 ADS1178