Datasheet

IN1
AINP1
AINN1
IN2
AINP2
AINN2
IN3
AINP3
AINN3
IN4
+3.3V
+1.8V
AINP4
AINN4
AVDD
DVDD
VREFP
VREFN
VCOM
TEST0
TEST1
DIN
AGND
DGND
IOVDD
CLK
DRDY/FSYNC
DVDD(I/O)
DR
FSR
DOUT1
SCLK
CVDD
(CORE)
DOUT2
DOUT3
DOUT4
SYNC
PWDN1 I/O
PWDN2
PWDN3
PWDN4
CLKDIV
FORMAT2
MODE
FORMAT1
FORMAT0
10 Fm
(2)
+
10 Fm
(2)
10 Fm
OPA350
+
0.1 Fm
(2)
0.1 Fm
(2)
100 Fm
+
0.1 Fm
(2)
100W1kW
REF1004
+5V
10 Fm
(2)
50W
+3.3V
(High-Speed,Frame-Sync,TDM,
andFixed-Positiondataselected.)
ADS1174 TMS320VC5509
200MHz
+1.6V
OPA1632
(1)
2.2nF
(3)
2.2nF
(3)
2.2nF
(3)
2.2nF
(3)
(4)
OPA350
Buffered
VCOM
Output
100W
1kW
100W
20kW
0.1 Fm
See
Note(5)
See
Note(6)
50W
U1
U2
CLKR
Q
Q
0
>
+3.3V
ADS1174
ADS1178
SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com
(1) External Schottky clamp diodes or series resistors may be needed to prevent overvoltage on the inputs. See the Analog Inputs section.
(2) Indicates ceramic capacitors.
(3) Indicates COG ceramic capacitors.
(4) For pin test mode, set to logic high.
(5) The op amp and input RC components filter the REF1004 noise.
(6) U1: SN74LVC1G04. U2: SN74LVC2G74. These components re-clock the ADS1174 data output to interface to the TMS320VC5509.
Figure 26. ADS1174 Basic Connection Circuit
26 Submit Documentation Feedback Copyright © 2007 – 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1174 ADS1178