Datasheet

SCLK
CS
(1)
DIN
DOUT
t
SCLK
t
CSSC
t
SPW
t
DIST
t
DIHD
t
SPW
t
CSDO
Hi-ZHi-Z
t
CSPW
t
DOPD
t
DOHD
DRDY
DOUT
t
DRDY
t
DDO
ADS1158
www.ti.com SBAS429D –JUNE 2008– REVISED MARCH 2011
PARAMETER MEASUREMENT INFORMATION
(1) CS can be tied low.
Figure 1. Serial Interface Timing
SERIAL INTERFACE TIMING CHARACTERISTICS
At T
A
= –40°C to +105°C and DVDD = 2.7V to 5.25V, unless otherwise noted.
SYMBOL DESCRIPTION MIN MAX UNITS
t
SCLK
SCLK period 2 τ
CLK
(1)
t
SPW
SCLK high or low pulse width (exceeding max resets SPI interface) 0.8 4096
(2)
τ
CLK
t
CSSC
CS low to first SCLK: setup time
(3)
2.5 τ
CLK
t
DIST
Valid DIN to SCLK rising edge: setup time 10 ns
t
DIHD
Valid DIN to SCLK rising edge: hold time 5 ns
t
DOPD
SCLK falling edge to valid new DOUT: propagation delay
(4)
20 ns
t
DOHD
SCLK falling edge to old DOUT invalid: hold time 0 ns
t
CSDO
CS high to DOUT invalid (3-state) 5 τ
CLK
t
CSPW
CS pulse width high 2 τ
CLK
(1) τ
CLK
= master clock period = 1/f
CLK
.
(2) Programmable to 256 τ
CLK
.
(3) CS can be tied low.
(4) DOUT load = 20pF || 100kΩ to DGND.
Figure 2. DRDY Update Timing
DRDY UPDATE TIMING CHARACTERISTICS
SYMBOL DESCRIPTION TYP UNITS
t
DRDY
DRDY high pulse width without data read 1 τ
CLK
t
DDO
Valid DOUT to DRDY falling edge (CS = 0) 0.5 τ
CLK
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