Datasheet

ADS1158
SBAS429D –JUNE 2008– REVISED MARCH 2011 www.ti.com
f. Clock Source: The ADS1158 requires a clock QFN/SON PCB Attachment for PCB layout
signal for operation. The clock can originate from recommendations, available for download at
either the crystal oscillator or from an external www.ti.com. The exposed thermal pad of the
clock source. The internal oscillator uses a PLL ADS1158 should be connected electrically to
circuit and an external 32.768kHz crystal to AVSS.
generate a 15.7MHz master clock. The PLL
requires a 22nF capacitor from the PLLCAP pin
CONFIGURATION GUIDE
to AVSS. The crystal and load capacitors should
Configuration of the ADS1158 involves setting the
be placed close to the pins as possible and kept
configuration registers via the SPI interface. After the
away from other traces with ac components. A
device is configured for operation, channel data are
buffered output of the 15.7MHz clock can be
read from the device through the same SPI interface.
used to drive other converters or controllers. An
The following procedure is recommended to configure
external clock source can be used up to 16MHz.
the device:
For best performance, the clock of the SPI
1. Reset the SPI Interface: Before using the SPI
interface controller and the converter itself should
interface, it may be necessary to recover the SPI
be on the same domain. This configuration
interface. To reset the interface, set CS high or
requires that the ratio of the SCLK to device clock
disable SCLK for 4096 (256) f
CLK
cycles.
must be limited to 1,1/2,1/4, 1/8, etc.
2. Stop the Converter: Set the START pin low to
g. Digital Inputs: It is recommended to source
stop the converter. Although not necessary for
terminate the digital inputs and outputs of the
configuration, this command stops the channel
device with a 50Ω (typical) series resistor. The
scanning sequence which then points to the first
resistors should be placed close to the driving
channel after configuration.
end of the source (output pins, oscillator, logic
gates, DSP, etc). This placement helps to reduce
3. Reset the Converter: The reset pin can be
the ringing and overshoot on the digital lines.
pulsed low or a Reset command can be sent.
Although not necessary for configuration, reset
h. Hardware Pins: START, DRDY, RESET, and
re-initializes the device into a known state.
PWDN. These pins allow direct pin control of the
ADS1158. The equivalent of the START and
4. Configure the Registers: The registers are
DRDY pins is provided via commands through
configured by writing to them either sequentially
the SPI interface; these pins may be left unused.
or as a group. The user may configure the
The device also has a RESET command. The
software in either mode. Any write to the
PWDN pin places the ADC into very low-power
Auto-Scan channel-select registers resets the
state where the device is inactive.
channel pointer to the channel of highest priority.
i. SPI Interface: The ADS1158 has an
5. Verify Register Data: The register data may be
SPI-compatible interface. This interface consists
read back for verification of device
of four signal lines: SCLK, DIN, DOUT, and CS.
communications.
When CS is high, the DIN input is ignored and
6. Start the Converter: The converter can be
the DOUT output 3-states. See Chip Select
started with the START pin or with a Pulse
(CS ) for more details. The SPI
Convert command sent through the interface.
interface can be operated in a minimum
7. Read Channel Data: The DRDY asserts low
configuration without the use of CS (tie CS low;
when data are ready. The channel data can be
see the Serial Interface and Communication
read at that time. If DRDY is not used, the
Protocol sections).
updated channel data can be checked by reading
j. GPIO: The ADS1158 has eight, user-
the NEW bit in the status byte. The status byte
programmable digital I/O pins. These pins are
also indicates the origin of the channel data. If
controlled by register settings. The register
the data for a given channel is not read before
setting is default to inputs. If these pins are not
DRDY asserts low again, the data for that
used, tie them high or low (do not float input pins)
channel is lost and replaced with new channel
or configure them as outputs.
data.
k. QFN Package: See Application Note SLUA271,
40 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS1158