Datasheet

DRDY
NEWBit
DataReads
(registerformat)
ADS1158
www.ti.com SBAS429D –JUNE 2008– REVISED MARCH 2011
CHANNEL DATA
The data read operation outputs either three bytes (one byte for status and two bytes for data), or two bytes for
data only. The selection of the 3-byte or 2-byte data read is set by the bit STAT in register CONFIG0 (see
Table 12, Status Byte, for options). In the 3-byte read, the first byte is the status byte and the following two bytes
are the data bytes. The MSB (Data15) of the data are shifted out first.
Table 9. CHANNEL DATA FORMAT
BYTE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
1 STATUS NEW OVF SUPPLY CHID4 CHID3 CHID2 CHID1 CHID0
2 MSB Data15 Data14 Data13 Data12 Data11 Data10 Data9 Data8
3 LSB Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data0
STATUS BYTE
BIT STATUS.7, NEW
The NEW bit is set when the results of a Channel Data Read Command returns new channel data. The bit
remains set indefinitely until the channel data are read. When the channel data are read again before the
converter updates with new data, the previous data are output and the NEW bit is cleared. If the channel data
are not read before the next conversion update, the data from the previous conversion is lost. As shown in
Figure 48, the NEW bit emulates the operation of the DRDY output pin. To emulate the function of the DRDY
output pin in software, the user reads data at a rate faster than the converter data rate. The user then polls the
NEW bit to detect for new channel data.
0 = Channel data have not been updated since the last read operation.
1 = Channel data have been updated since the last read operation.
Figure 48. NEW Bit Operation
BIT STATUS.6, OVF
When this bit is set, it indicates that the differential voltage applied to the ADC inputs have exceeded the range
of the converter |V
IN
| > 1.06V
REF
. During over-range, the output code of the converter clips to either positive FS
(V
IN
≥ 1.06 × V
REF
) or negative FS (V
IN
≤ –1.06 × V
REF
). This bit, with the MSB of the data, can be used to
detect positive or negative over-range conditions. Note that because of averaging incorporated within the digital
filter, the absence of this bit does not assure that the modulator of the ADC has not saturated as a result of
possible transient input overload conditions.
BIT STATUS.5, SUPPLY
This bit indicates that the analog power-supply voltage (AVDD – AVSS) is below a preset limit. The SUPPLY bit
is set when the value falls below 4.3V (typically) and is reset when the value rises 50mV higher (typically) than
the lower trip point. The output data of the ADC may not be valid under low power-supply conditions.
BITS CHID[4:0] CHANNEL ID BITS
The Channel ID bits indicate the measurement channel of the acquired data. Note that for Fixed-Channel mode,
the Channel ID bits are undefined. See Table 10 for the channel ID, the measurement priority, and the channel
description for Auto-Scan Mode.
Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): ADS1158