Datasheet

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
CS
SCLK
DIN
CommandByte RegisterData
(1)
RegisterData
(1)(2)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
CS
SCLK
DIN
Command1 Command2
(1)
Command3
(1)
ADS1158
SBAS429D –JUNE 2008– REVISED MARCH 2011 www.ti.com
Register Read Command
Beginning with the eighth SCLK rising edge
(command byte completed), the MSB of the data are
To read register data, the first three bits of the
shifted in. The remaining seven SCLK rising edges
command byte to be shifted into the device are 010.
complete the write to a single register. If MUL = '1',
These bits are followed by the multiple register read
the data to the next register can be written by
bit (MUL). If MUL = '1', then multiple registers can be
supplying additional SCLKs. The operation terminates
read in sequence beyond the desired register. If
when the last register is accessed (address = 09h),
MUL = '0', only data from the addressed register can
as shown in Figure 46.
be read. The last four bits of the command word are
the beginning register address bits. During this time,
CONTROL COMMANDS
the invalid data may appear on DOUT until the
command is completed. These data should be
Pulse Convert Command
ignored. Beginning with the eighth falling edge of
SCLK (command byte completed), the MSB of the
See Conversion Control section.
register data are output on DOUT. The remaining
eight SCLK transitions complete the read of a single
Reset Command
register. If MUL = '1', the data from the next register
The Reset command resets the ADC. All registers
can be read in sequence by supplying additional
are reset to their default values. A conversion in
SCLKs. The operation terminates when the last
process continues but will be invalid when completed
register is accessed (address = 09h); see Figure 45.
(DRDY low). This conversion data should be
discarded. Note that the SPI interface may require
Register Write Command
reset for this command, or any command, to function.
To write register data, the first three bits of the
To ensure device reset under a possible locked SPI
command byte to be shifted into the device are 011.
interface condition, do one of the following: 1) toggle
These bits are followed by the multiple register read
CS high then low and send the reset command; or 2)
bit (MUL). If MUL = '1', then multiple registers can be
hold SCLK inactive for 256/f
CLK
or 4096/f
CLK
and send
written in sequence beyond the desired register. If
the reset command. The control commands are
MUL = '0', only data to the addressed register can be
illustrated in Figure 47.
written. The remaining four bits of the command word
are the beginning register address bits. During this
time, the invalid data may appear on DOUT until the
command is completed. These data should be
ignored.
(1) One or more bytes, depending on MUL bit.
(2) After the prescribed number of registers are read, then one or more additional commands can be issued in succession.
Figure 46. Register Write Operation
(1) One or more additional commands can be issued in succession.
Figure 47. Control Command Operation
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