Datasheet

DRDY
DRDY
SCLK
SCLK
DRDY withSCLK
DRDY withoutSCLK
t
DRDYPLS
t =
DRDYPLS
1
f
CLK
ADS1158
www.ti.com SBAS429D –JUNE 2008– REVISED MARCH 2011
Data Ready Output (DRDY)
DRDY is usually connected to an interrupt of a
controller, DSP, or connected to a controller port pin
The DRDY pin is an output that asserts low to
for polling in a software loop. Channel data can be
indicate when new channel data are available to read
read without the use of DRDY. Read the data using
(the previous conversion data are lost). DRDY returns
the register format read and check the Status Byte
high after the first falling edge of SCLK during a data
when the NEW bit = 1, which indicates new channel
read operation. If the data are not read (no SCLK
data.
pulses), DRDY remains low until new channel data
are available once again. DRDY then pulses high,
Output Data Scaling and Over-Range
then low to indicate new data are available; see
Figure 39.
The ADS1158 is scaled such that the output data
code resulting from an input voltage equal to ±V
REF
has a margin of 6.6% before clipping. This
architecture allows operation of applied input signals
at or near full-scale without overloading the converter.
Specifically, the device is calibrated so that:
1LSB = V
REF
/7800h,
and the output clips when:
|V
IN
| ≥ 1.06 × V
REF
.
Table 7 summarizes the ideal output codes versus
input signals.
Figure 39. DRDY Timing
(See Figure 2 for the DRDY Pulse)
Table 7. Ideal Output Code versus Input Signal
INPUT SIGNAL V
IN
(ADCINP – ADCINN) IDEAL OUTPUT CODE
(1)
DESCRIPTION
≥ +1.06 V
REF
7FFFh Maximum positive full-scale before output clipping
+V
REF
7800h V
IN
= +V
REF
+1.06 V
REF
/(2
15
– 1) 0001h +1LSB
0 0000h Bipolar Zero
–1.06 V
REF
/(2
15
– 1) FFFFh –1LSB
–V
REF
87FFh V
IN
= –V
REF
≤ –1.06 V
REF
× (2
15
/2
15
– 1) 8000h Maximum negative full-scale before output clipping
(1) Ideal output code –0.5LSB excludes effects of noise, linearity, offset, and gain errors.
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